Spintronics primitive gate with high error correction efficiency 6(P error) 2 for logic-in memory architecture

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 63-64

  Tsuji, Y ^a   Nebashi, R ^a   Sakimura, N ^a   Morioka, A ^a   Honjo, H ^a   Tokutome, K ^a   Miura, S ^a   Suzuki, T ^b   Fukami, S ^c   Kinoshita, K ^c   Hanyu, T ^c   Endoh, T ^c   Kasai, N ^c   Ohno, H ^c   Sugibayashi, T ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CURRENT PATHS; DOMAIN WALL MOTION; ERROR RATE; PATH TRANSISTORS;

CELLS; CYTOLOGY; ERROR CORRECTION; MAGNETOELECTRONICS; NANOTECHNOLOGY; REDUNDANCY;

MEMORY ARCHITECTURE;

EID: 84866534795     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242462     Document Type: Conference Paper

References (5)

1. W. H. Kautz et al., Trans. of Computers C-18, 719, 1969.
2. N. Sakimura et al., JSSC 44, 2244, 2009.
3. S. Patil et al., ICCD, 125, 2010.
4. H. Honjo et al., Journal of Applied Physics, to be published, 2012.
5. N. Sakimura et al., ISCAS, to be published, 2012.