Worst case switching pattern for core noise analysis

Designcon 2009

Volumn 1, Issue , 2009, Pages 258-272

  Cheng, Wheling ^a   Sarkar, Aveek ^b,c   Lin, Shen ^b   Zheng, Ji ^b  

^a CISCO SYSTEMS   (United States)

^b Engineering   (United States)

^c NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; FREQUENCY CONTENTS; NOISE ANALYSIS; POWER DELIVERY NETWORK; POWER INTEGRITY; PROCESS FLOWS; RESONANCE FREQUENCIES; SWITCHING ACTIVITIES; SWITCHING PATTERNS; WORST CASE PATTERN;

ELECTRIC POWER TRANSMISSION; INTEGRATED CIRCUITS; NATURAL FREQUENCIES;

SWITCHING;

EID: 84866344744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Lin, et al "Full-chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100uV/100ps-Resolution Measurement", CICC, 2004.S