Silicon based SiP with crude through wafer vias

IMAPS Nordic Annual Conference 2006

Volumn , Issue , 2006, Pages 135-141

  Rodenburg, E C ^a   Van Grunsven, E C E ^a   Aumaille, K ^b   Ledain, S ^b   Bunel, C ^b   Van Der Wel, P ^b   Den Dekker, A ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE ELEMENTS; ASSEMBLY PROCESS; BACKSIDE METAL; BACKSIDE METALLIZATION; FRONT-END PROCESS; HIGH FREQUENCY PERFORMANCE; INTEGRATED SUBSTRATE; LEAD FRAME; METAL THICKNESS; MINIMUM RESISTANCE; PASSIVE INTEGRATION; PHILIPS; RELIABILITY EVALUATION; RF PERFORMANCE; SERIES RESISTANCES; SILICON CARRIERS; SILICON-BASED; STEP COVERAGE; SYSTEM IN PACKAGE TECHNOLOGIES; TEMPERATURE CYCLE TEST; THROUGH-WAFER VIAS; WAFER THINNING;

ELECTRIC RESISTANCE; INDUCTANCE; INTEGRATION; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; SUBSTRATES;

SILICON WAFERS;

EID: 84866325456     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. th European Microelectronics and Packaging Conference and exhibition, Brugge, Belgium, 12-15 June, 2005.
2. F. Lärmer, A. Schilp, US patent 5, 501, 893, March 26, 1996.
3. Franck Murray, "Silicon based System-in-Package: a passive integration technology combined with advanced packaging and system based design tools to allow a breakthrough in miniaturization", Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2005), proceedings, 169-173, 2005.
4. F. Roozeboom and al, "Passive and heterogeneous integration towards a Si-based System-in-package concept", Thin Solid Films, 504, 391-396, 2006.
5. F. Roozeboom and al, "High density, Low-Loss MOS Capacitors for integrated RF Decoupling", Int. J. Microcircuits and Electronic Packaging, 24 (3),182-196, 2001.
6. F. Roozeboom and al, "Low-Loss MOS Decoupling Capacitors integrated in a GSM Power Amplifier", Mat. Res. Soc. Symp. Proc. 783, 157-162, 2003.