Designing fast LTL model checking algorithms for many-core GPUs

Journal of Parallel and Distributed Computing

Volumn 72, Issue 9, 2012, Pages 1083-1097

  Barnat, Jiří ^a   Bauch, Petr ^a   Brim, Luboš ^a   Češka, Milan ^a  

^a MASARYK UNIVERSITY   (Czech Republic)

Author keywords

CUDA technology; Linear temporal logic; Massively parallel architectures; Multiple CUDA devices; Parallel model checking

Indexed keywords

COMPUTATION THEORY; DATA STRUCTURES; DISTRIBUTED COMPUTER SYSTEMS; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; TEMPORAL LOGIC;

COMPACT DATA STRUCTURE; CUDA TECHNOLOGIES; EXPERIMENTAL EVALUATION; LINEAR TEMPORAL LOGIC; MULTIPLE CUDA DEVICES; PARALLEL MODEL CHECKING; STATE-SPACE GENERATION; TECHNOLOGICAL DEVELOPMENT;

MODEL CHECKING;

EID: 84864845053     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2011.10.015     Document Type: Article

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