Generation of systemC/TLM code from UML/MARTE sequence diagrams for verification

Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012

Volumn , Issue , 2012, Pages 187-190

  Ebeid, Emad ^a   Quaglia, Davide ^a   Fummi, Franco ^a  

^a UNIVERSITY OF VERONA   (Italy)

Author keywords

MARTE; Sequence diagram; SystemC TLM; timing constraint; UML; VSL

Indexed keywords

MARTE; SEQUENCE DIAGRAMS; SYSTEMC; TIMING CONSTRAINTS; UML; VSL;

DESIGN; ELECTRIC NETWORK SYNTHESIS; TIMING CIRCUITS;

MODEL CHECKING;

EID: 84864351583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2012.6219051     Document Type: Conference Paper

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