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Volumn , Issue , 2012, Pages 11-12
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Tensile strained Ge layers obtained via a Si-CMOS compatible approach
a,b
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Author keywords
[No Author keywords available]
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Indexed keywords
ACTIVE LAYER;
ACTIVE MATERIAL;
ACTIVE REGIONS;
ANALOG CIRCUITRY;
BLANKET STRUCTURES;
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES;
COMPRESSIVE STRAIN;
CVD REACTORS;
CW OPERATION;
DONOR DENSITY;
DOPANT ACTIVATION;
FABRICATION METHOD;
FABRICATION PROCESS;
FABRY-PEROT OSCILLATIONS;
FINITE ELEMENT METHOD SIMULATION;
GROWTH PROCESS;
HETEROEPITAXIAL LAYERS;
HIGH SPEED DETECTORS;
LIGHT EMITTERS;
LIGHT EMITTING DEVICES;
MASS PRODUCTION;
MATERIAL PROCESSING;
MATERIAL SYSTEMS;
MAXIMUM GAIN;
MICRO RAMAN SPECTROSCOPY;
MICRO-MECHANICAL;
MONOLITHIC INTEGRATION;
N-DOPING;
N-TYPE DOPING;
ON-CHIP INTEGRATION;
OPTICALLY PUMPED;
PHOTONIC COMPONENTS;
PL EMISSION;
PL SPECTRA;
PRODUCTION PROCESS;
RED-SHIFTED;
RESIDUAL TENSILE STRAIN;
ROOM TEMPERATURE;
ROOM-TEMPERATURE PHOTOLUMINESCENCE;
SI PHOTONICS;
SOI SUBSTRATES;
STANDARD CMOS PROCESS;
STRAIN DISTRIBUTIONS;
STRAINED-GE;
ANALOG CIRCUITS;
CMOS INTEGRATED CIRCUITS;
EPITAXIAL GROWTH;
FABRICATION;
GERMANIUM;
INTEGRATION;
LIGHT SOURCES;
LITHOGRAPHY;
MATERIALS;
MODULATORS;
OPTICAL GAIN;
OPTICALLY PUMPED LASERS;
PHOTONICS;
PRODUCTION ENGINEERING;
PUMPING (LASER);
RAMAN SPECTROSCOPY;
SEMICONDUCTOR DEVICE MANUFACTURE;
SILICON;
SILICON NITRIDE;
SILICON WAFERS;
SUBSTRATES;
TENSILE STRAIN;
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EID: 84864251845
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISTDM.2012.6222428 Document Type: Conference Paper |
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Times cited : (6)
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References (8)
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