Towards automated proof of fail-safe behavior

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1516, Issue , 1998, Pages 169-184

  Liggesmeyer, Peter ^a   Rothfelder, Martin ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL VERIFICATION; RISK ANALYSIS; RISK ASSESSMENT; SAFETY ENGINEERING;

AUTOMATED PROOFS; AUTOMATIC GENERATION; FAULT-TREES; FUNCTIONAL ASPECTS; INPUT AND OUTPUTS; ITS APPLICATIONS; SAFETY FUNCTIONS; SYSTEM INTEGRITY;

FAULT TREE ANALYSIS;

EID: 84863957317     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49646-7_13     Document Type: Conference Paper

References (13)

1. Akers S. B. Binary Decision Diagrams, IEEE Trans. Comp. Vol. C-27, No. 6, June 1978, pp. 509–516
2. Allen D. J. Digraphs and Fault Trees, Hazard Prevention January/February 1983, pp. 22-25
3. Bader P., Päppinghaus P., Pichler C., Schmid R., Umbreit G., Winkelmann K. CSL Referenzmanual – Sprachbeschreibung, Internal Report, Siemens AG, München, 1996
4. Bollig B., Wegener I. Improving the Variable Ordering of OBDDs is NP-Complete, IEEE Trans. Comp., Vol. 45, No. 9, September 1996, pp. 993–1001
5. Bormann J., Lohse J., Payer M., Venzl G. Model Checking in Industrial Hardware Design, 32nd ACM/IEEE Design Automation Conference 1995
6. Bryant R. E. Graph-Based Algorithms for Boolean Function Manipulation, IEEE Trans. Comp., Vol. C-35, No.8, August 1986, pp. 667–691
7. Bryant R. E. Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams, ACM Computing Surveys, Vol. 24, No.3, September 1992, pp. 293–318
8. Burch J. R., Clarke E. M., Long D. E., McMillan K. L., Dill D. L. Symbolic Model Checking for Sequential Circuit Verification, IEEE Design & Test, Vol. 13 No. 4, April 1994, pp. 401–424
9. Campos S., Clarke E., Marrero W., Minea M. Timing analysis of industrial real-time systems, In: Workshop on Industrial Strength Formal Specification Techniques, 1995.
10. Filkorn T., Schneider H.-A., Scholz A., Strasser A., Warkentin P. SVE Users’ Guide, Internal Report, Siemens AG, München, 1996
11. Lee C. Y. Representation of Switching Circuits by Binary-Decision Programs, The Bell System Technical Journal 38, July 1959, pp. 985–999
12. Lewerentz C., Lindner T. Formal Development of Reactive Systems: Case Study Production Cell, LNCS 891, Springer-Verlag, January 1995
13. Liggesmeyer P., Rothfelder M. Improving System Reliability with Automatic Fault Tree Generation, Proc. FTCS-28, Munich, Germany, 1998, pp. 90–99