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Volumn 1998-January, Issue , 1998, Pages 90-99

Improving system reliability with automatic fault tree generation

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; RISK ANALYSIS; RISK ASSESSMENT;

EID: 85043391611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FTCS.1998.689458     Document Type: Conference Paper
Times cited : (44)

References (16)
  • 1
    • 0017983865 scopus 로고
    • Binary decision diagrams
    • June
    • Akers S. B. Binary Decision Diagrams, IEEE Trans. Comp. vol. C-27, No. 6, June 1978, pp. 509-516
    • (1978) IEEE Trans. Comp. , vol.C-27 , Issue.6 , pp. 509-516
    • Akers, S.B.1
  • 2
    • 84948973835 scopus 로고
    • Hazard Prevention January/February
    • Allen D. J. Digraphs and Fault Trees, Hazard Prevention January/February 1983, pp. 22-25
    • (1983) Digraphs and Fault Trees , pp. 22-25
    • Allen, D.J.1
  • 4
    • 0030246260 scopus 로고    scopus 로고
    • Improving the variable ordering of OBDDs is NP-complete
    • September
    • Bollig B., Wegener I. Improving the Variable Ordering of OBDDs is NP-Complete, IEEE Trans. Comp., Vol. 45, No. 9, September 1996, pp. 993-1001
    • (1996) IEEE Trans. Comp. , vol.45 , Issue.9 , pp. 993-1001
    • Bollig, B.1    Wegener, I.2
  • 6
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • August
    • Bryant R. E. Graph-Based Algorithms for Boolean Function Manipulation, IEEE Trans. Comp., vol. C-35, No. 8, August 1986, pp. 667-691
    • (1986) IEEE Trans. Comp. , vol.C-35 , Issue.8 , pp. 667-691
    • Bryant, R.E.1
  • 7
    • 0026913667 scopus 로고
    • Symbolic Boolean manipulation with ordered binary-decision diagrams
    • September
    • Bryant R. E. Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams, ACM Computing Surveys, Vol. 24, No. 3, September 1992, pp. 293-318
    • (1992) ACM Computing Surveys , vol.24 , Issue.3 , pp. 293-318
    • Bryant, R.E.1
  • 8
    • 0028413136 scopus 로고
    • Symbolic model checking for sequential circuit verification
    • April
    • Burch J. R., Clarke E. M., Long D. E., McMillan, K. L. Dill D. L. Symbolic Model Checking for Sequential Circuit Verification, IEEE Design & Test, Vol. 13 No. 4, April 1994, pp. 401-424
    • (1994) IEEE Design & Test , vol.13 , Issue.4 , pp. 401-424
    • Burch, J.R.1    Clarke, E.M.2    Long, D.E.3    McMillan, K.L.4    Dill, D.L.5
  • 13
    • 84903828974 scopus 로고
    • Representation of switching circuits by binary-decision programs
    • July
    • Lee C. Y. Representation of Switching Circuits by Binary-Decision Programs, The Bell System Technical Journal 38, July 1959, pp. 985-999
    • (1959) The Bell System Technical Journal , vol.38 , pp. 985-999
    • Lee, C.Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.