A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA

SPL 2012 - 8th Southern Programmable Logic Conference

Volumn , Issue , 2012, Pages

  Pedre, Sol ^a   Krajník, Tomáš ^b   Todorovich, Elías ^c   Borensztejn, Patricia ^a  

^a UNIVERSIDAD DE BUENOS AIRES   (Argentina)

^b CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

^c UNIVERSIDAD NACIONAL DEL CENTRO DE LA PROVINCIA DE BUENOS AIRES   (Argentina)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; CO-DESIGN FLOW; CO-DESIGN METHODOLOGY; CODE LINE; DESIGN APPROACHES; DESIGN EFFORT; DESIGN METHOD; EXACT METHODS; HARDWARE ACCELERATION; HARDWARE IMPLEMENTATIONS; HARDWARE-ACCELERATED; HIGH-LEVEL MODELING; MULTIPLE ROBOT; PROFILING TOOLS; REAL-TIME IMAGE PROCESSING; REFERENCE MODELS; SOFTWARE CODING; SOFTWARE DOMAINS; SOFTWARE SOLUTION;

DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENGINEERS; IMAGE PROCESSING; ROBOT APPLICATIONS;

HARDWARE;

EID: 84863921327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPL.2012.6211770     Document Type: Conference Paper

References (24)

1. B. Bailey, G. Martin, and A. Piziali, ESL Design and Verification: A prescription for Electronic System-Level Methodology. Morgan Kaufmann, 2007.
2. B. Bailey and G. Martin, ESL Models and their Application. Electronic System Level Design and Verification in Practice. Springer, 2010.
3. A. Jerraya and W. Wolf, "Hardware/software interface codesign for embedded systems," Computer, vol. 38, no. 2, pp. 63-69, Feb. 2005.
4. T. Jeremiassen, T. Kogel, A. Takach, G. Martin, and A. Donlin, "From ESL 2010 to ESL 2015," in Hardware/Software Codesign and System Synthesis, Scottsdale, Arizona, USA, 2010, pp. 61-62.
5. Reinaldo Bergamaschi et al., "The State of ESL Design [Roundtable]," IEEE Design & Test of Computers, vol. 25, no. 6, pp. 510-519, 2008.
6. M. Santarini, "Zynq-7000 EPP sets stage for new era of innovations," Xcell Journal, vol. 75, pp. 8-13, May 2011.
7. J. Gaisler, "A structured VHDL design method," in Fault-tolerant Microprocessors for Space Applications. Gaisler Research, pp. 41-50. [Online]. Available: http://www.gaisler.com/doc/vhdl2proc.pdf
8. W. Mueller, A. Rosti, S. Bocchio, E. Riccobene, P. Scandurra, W. Dehaene, Y. Vanderperren, and L. Ku, "UML for ESL Design - Basic Principles, Tools, and Applications," in 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, Nov. 2006, pp. 73-80.
9. E. Riccobene and P. Scandurra, "Weaving executability into UML class models at PIM level," in First European Workshop on Behaviour Modelling in Model Driven Architecture (BM-MDA). Enschede, The Netherlands: CTIT Workshop Proceedings Series, 2009, pp. 10-28.
10. F. Mallet, C. André, and J. DeAntoni, "Executing AADL Models with UML/MARTE," in International Conference of Engineering of Complex Computer Systems, no. June. Germany: IEEE, 2009, pp. 371-376.
11. A.G. Silva-Filho et al., "An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms," International Journal of Reconfigurable Computing, vol. 2011, pp. 1-12, 2011.
12. Jacquard Computing. (2011, Oct.) ROCCC 2.0. [Online]. Available: http://www.jacquardcomputing.com/roccc/
13. S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "SPARK: A High-Level Synthesis Framework For Applying Parallelizing Compiler Transformations," in 16th Intl. Conf. on VLSI Design. IEEE, 2003, pp. 461-467.
14. Y. Yankova, G. Kuzmanov, K. Bertels, G. Gaydadjiev, Y. Lu, and S. Vassiliadis, "DWARV : Delftworkbench automated reconfigurable VHDL generator," in Intl Conf on Field Programmable Logic and Applications. IEEE, 2007, pp. 697-701.
15. Nallatech. (2011, Oct.) DIME-C Ansi-C to VHDL compiler. [Online]. Available: http://www.nallatech.com/Development-Tools/dime-c.html
16. S. Computers. (2011, Oct.) Carte Programming Environment. [Online]. Available: http://www.srccomp.com/techpubs/carte.asp
17. M. Graphics. (2011, Oct.) CatapultC synthesis. [Online]. Available: http://www.mentor.com/esl/catapult/overview
18. A.J. Virginia et al., "An empirical comparison of ANSI-C to VHDL compilers : SPARK, RORCC and DWARV," in Anual Workshop on Circuits Systems and Signal Processing ProRISC, 2007, pp. 388-394.
19. ESA. (2011, Oct.) ESA Microelectronics VHDL. [Online]. Available: http://www.esa.int/TEC/ Microelectronics/SEMS7EV681F 0.html
20. J. Gaisler. (2011, Oct.) A structured VHDL Design Method. [Online]. Available: http://www.gaisler.com/doc/structdes.pdf
21. Sparx Systems. (2011, Oct.) Visual Modelling Platform. [Online]. Available: http://www.sparxsystems.com/products/ea/
22. Xilinx. (2011, Oct.) Platform Studio and the Embedded Development Kit (EDK). [Online]. Available: http://www.xilinx.com/tools/platform.htm
23. M. Kulich et al., "SyRoTek - On an e-Learning System for Mobile Robotics and Artificial Intelligence," in ICAART 2009, vol. 1. Setúbal: INSTICC Press, 2009, pp. 275-280, http://syrotek.felk.cvut.cz.
24. Xilinx. (2011, Oct.) PowerPC 405 Processor Block Reference Guide. [Online]. Available: http://www.xilinx.com/support /documentation/user guides/ug018.pdf