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Volumn , Issue , 2009, Pages 371-376

Executing AADL models with UML/MARTE

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; REAL TIME SYSTEMS; SEMANTICS; UNIFIED MODELING LANGUAGE;

EID: 70350070603     PISSN: 27708527     EISSN: 27708535     Source Type: Conference Proceeding    
DOI: 10.1109/ICECCS.2009.10     Document Type: Conference Paper
Times cited : (16)

References (14)
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    • The ProMARTE Consortium, Object Management Group, June, OMG document number: ptc/08-06-08
    • The ProMARTE Consortium, UML Profile for MARTE, beta 2, Object Management Group, June 2008, OMG document number: ptc/08-06-08.
    • (2008) UML Profile for MARTE, beta 2
  • 3
    • 85178851996 scopus 로고    scopus 로고
    • F. Singhoff and A. Plantec, AADL modeling and analysis of hierarchical schedulers, in SIGAda, A. Srivastava and L. C. B. III, Eds. ACM, 2007, pp. 41-50.
    • F. Singhoff and A. Plantec, "AADL modeling and analysis of hierarchical schedulers," in SIGAda, A. Srivastava and L. C. B. III, Eds. ACM, 2007, pp. 41-50.
  • 4
    • 46749130116 scopus 로고    scopus 로고
    • Marte: Also an UML profile for modeling AADL applications
    • IEEE Computer Society
    • M. Faugère, T. Bourbeau, R. de Simone, and S. Gérard, "Marte: Also an UML profile for modeling AADL applications," in ICECCS - UML&AADL. IEEE Computer Society, 2007, pp. 359-364.
    • (2007) ICECCS - UML&AADL , pp. 359-364
    • Faugère, M.1    Bourbeau, T.2    de Simone, R.3    Gérard, S.4
  • 5
    • 44149124559 scopus 로고    scopus 로고
    • Dealing with AADL end-to-end flow latency with UML Marte
    • IEEE CS, April
    • S.-Y. Lee, F. Mallet, and R. de Simone, "Dealing with AADL end-to-end flow latency with UML Marte," in ICECCS - UML&AADL. IEEE CS, April 2008, pp. 228-233.
    • (2008) ICECCS - UML&AADL , pp. 228-233
    • Lee, S.-Y.1    Mallet, F.2    de Simone, R.3
  • 6
    • 78651577630 scopus 로고    scopus 로고
    • Modeling of AADL data-communications with UML Marte
    • Springer, May, ch. 11, pp
    • C. André, F. Mallet, and R. de Simone, Modeling of AADL data-communications with UML Marte, ser. LNEE. Springer, May 2008, vol. 10, ch. 11, pp. 150-170.
    • (2008) ser. LNEE , vol.10 , pp. 150-170
    • André, C.1    Mallet, F.2    de Simone, R.3
  • 7
    • 85089791426 scopus 로고    scopus 로고
    • Event-triggered vs. time-triggered communications with UML Marte
    • IEEE
    • F. Mallet, R. de Simone, and L. Rioux, "Event-triggered vs. time-triggered communications with UML Marte," in FDL. IEEE, 2008, pp. 154-159.
    • (2008) FDL , pp. 154-159
    • Mallet, F.1    de Simone, R.2    Rioux, L.3
  • 8
    • 52949119512 scopus 로고    scopus 로고
    • CCSL: Specifying clock constraints with UML/Marte
    • F. Mallet, "CCSL: specifying clock constraints with UML/Marte," ISSE, vol. 4, no. 3, pp. 309-314, 2008.
    • (2008) ISSE , vol.4 , Issue.3 , pp. 309-314
    • Mallet, F.1
  • 9
    • 38849136470 scopus 로고    scopus 로고
    • Virtual execution of aadl models via a translation into synchronous programs
    • C. M. Kirsch and R. Wilhelm, Eds. ACM
    • E. Jahier, N. Halbwachs, P. Raymond, X. Nicollin, and D. Lesens, "Virtual execution of aadl models via a translation into synchronous programs," in EMSOFT, C. M. Kirsch and R. Wilhelm, Eds. ACM, 2007, pp. 134-143.
    • (2007) EMSOFT , pp. 134-143
    • Jahier, E.1    Halbwachs, N.2    Raymond, P.3    Nicollin, X.4    Lesens, D.5
  • 10
    • 51349136631 scopus 로고    scopus 로고
    • Virtual prototyping aadl architectures in a polychronous model of computation
    • IEEE Computer Society
    • M. Yue, J.-P. Talpin, and T. Gautier, "Virtual prototyping aadl architectures in a polychronous model of computation," in MEMOCODE. IEEE Computer Society, 2008, pp. 139-148.
    • (2008) MEMOCODE , pp. 139-148
    • Yue, M.1    Talpin, J.-P.2    Gautier, T.3
  • 11
    • 85178864201 scopus 로고    scopus 로고
    • P. H. Feiler and J. Hansson, Flow latency analysis with the architecture analysis and design language, CMU, Tech. Rep. CMU/SEI-2007-TN-010, June 2007.
    • P. H. Feiler and J. Hansson, "Flow latency analysis with the architecture analysis and design language," CMU, Tech. Rep. CMU/SEI-2007-TN-010, June 2007.
  • 13
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    • IEEE Standards Association, IEEE Standard for Verilog Hardware Description Language, Design Automation Standards Committee, 2005, IEEE Std 1364TM-2005.
    • IEEE Standards Association, IEEE Standard for Verilog Hardware Description Language, Design Automation Standards Committee, 2005, IEEE Std 1364TM-2005.
  • 14
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    • N. Feiertag, K. Richter, J. Nordlander, and J. Jonsson, A compositional framework for end-to-end path delay calculation of automotive sytems under different path semantics, Work. on Compositional Theory and Technology for Real-Time Embedded Systems CRTS, Barcelona (E), 2008.
    • N. Feiertag, K. Richter, J. Nordlander, and J. Jonsson, "A compositional framework for end-to-end path delay calculation of automotive sytems under different path semantics," Work. on Compositional Theory and Technology for Real-Time Embedded Systems CRTS, Barcelona (E), 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.