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Volumn 376 AICT, Issue , 2012, Pages 287-298

A small depth-16 circuit for the AES S-box

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHIC APPLICATIONS; NUMBER OF GATES;

EID: 84863895586     PISSN: 18684238     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-30436-1_24     Document Type: Conference Paper
Times cited : (88)

References (16)
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    • Boyar, J., Peralta, R., Pochuev, D.: On the multiplicative complexity of Boolean functions over the basis (∧, ⊕, 1). Theoretical Computer Science 235, 43-57 (2000)
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  • 3
    • 27244440344 scopus 로고    scopus 로고
    • A Very Compact S-Box for AES
    • Rao, J.R., Sunar, B. (eds.) CHES 2005. Springer, Heidelberg
    • Canright, D.: A Very Compact S-Box for AES. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 441-455. Springer, Heidelberg (2005)
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    • Canright, D.1
  • 4
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    • Tech. Rep. NPS-MA-05-001, Naval Postgraduate School
    • Canright, D.: A very compact Rijndael S-box. Tech. Rep. NPS-MA-05-001, Naval Postgraduate School (2005)
    • (2005) A Very Compact Rijndael S-box
    • Canright, D.1
  • 5
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    • Solving circuit optimisation problems in cryptography and cryptanalysis
    • ePrint Archive 2011
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    • (2011) IACR Cryptology , vol.475
    • Courtois, N.1    Hulme, D.2    Mourouzis, T.3
  • 6
    • 77954969533 scopus 로고    scopus 로고
    • Synthesizing Shortest Linear Straight-Line Programs over GF(2) Using SAT
    • Strichman, O., Szeider, S. (eds.) SAT 2010. Springer, Heidelberg
    • Fuhs, C., Schneider-Kamp, P.: Synthesizing Shortest Linear Straight-Line Programs over GF(2) Using SAT. In: Strichman, O., Szeider, S. (eds.) SAT 2010. LNCS, vol. 6175, pp. 71-84. Springer, Heidelberg (2010)
    • (2010) LNCS , vol.6175 , pp. 71-84
    • Fuhs, C.1    Schneider-Kamp, P.2
  • 8
    • 0000827611 scopus 로고
    • m) using normal bases
    • m) using normal bases. Inf. Comput. 78(3), 171-177 (1988)
    • (1988) Inf. Comput. , vol.78 , Issue.3 , pp. 171-177
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  • 9
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    • A method of circuit synthesis
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  • 10
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    • An Optimized S-Box Circuit Architecture for Low Power AES Design
    • Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. Springer, Heidelberg
    • Morioka, S., Satoh, A.: An Optimized S-Box Circuit Architecture for Low Power AES Design. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 172-186. Springer, Heidelberg (2003)
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    • Morioka, S.1    Satoh, A.2
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  • 12
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    • 2) and Conversion Matrices of Subbytes of AES
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    • 2) and Conversion Matrices of Subbytes of AES. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 234-247. Springer, Heidelberg (2010)
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    • Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A Compact Rijndael Hardware Architecture with S-Box Optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239-254. Springer, Heidelberg (2001)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.