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Volumn 6049 LNCS, Issue , 2010, Pages 178-189

A new combinational logic minimization technique with applications to cryptology

Author keywords

AES; Circuit complexity; Linear component minimization; Multiplicative complexity; S box

Indexed keywords

AES; CIRCUIT COMPLEXITY; LINEAR COMPONENTS; MULTIPLICATIVE COMPLEXITY; S-BOX;

EID: 77954990110     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-13193-6_16     Document Type: Conference Paper
Times cited : (126)

References (12)
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    • Boyar, J.1    Peralta, R.2
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    • A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
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    • Some remarks on efficient inversion in finite fields
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    • A compact rijndael hardware architecture with S-box optimization
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    • Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact rijndael hardware architecture with S-box optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239-254. Springer, Heidelberg (2001).
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.