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Volumn , Issue , 2011, Pages 373-375

A simulator for flexible sensor nodes in wireless networks

Author keywords

FPGA; sensor nodes; Simulator; wireless sensor network

Indexed keywords

CO-PROCESSORS; COMPUTE-INTENSIVE TASKS; CURRENT SENSORS; EXECUTION SPEED; FLEXIBLE SENSOR; PEAK PERFORMANCE; WIRELESS SENSOR;

EID: 84862940316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MSN.2011.93     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 2
    • 80051986939 scopus 로고    scopus 로고
    • A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes
    • S. Iyer, J. Zhang, Y. Yang, and P. Schaumont. A Unifying Interface Abstraction for Accelerated Computing in Sensor Nodes. In EslSyn, 2011.
    • (2011) EslSyn
    • Iyer, S.1    Zhang, J.2    Yang, Y.3    Schaumont, P.4
  • 3
    • 34548854494 scopus 로고    scopus 로고
    • A Reconfigurable Fpga-based Architecture for Modular Nodes in Wireless Sensor Networks
    • IEEE Press, Mar del Plata
    • Portilla J., Riesgo T., and de Castro A.: A Reconfigurable Fpga-based Architecture for Modular Nodes in Wireless Sensor Networks. In: 3rd Southern Conference on Programmable Logic, pp. 203-206. IEEE Press, Mar del Plata (2007).
    • (2007) 3rd Southern Conference on Programmable Logic , pp. 203-206
    • Portilla, J.1    Riesgo, T.2    De Castro, A.3
  • 4
    • 79960997045 scopus 로고    scopus 로고
    • Embedded Run-time Reconfigurable Nodes for Wireless Sensor Networks Applications
    • Krasteva Y. E., Portilla J., de la Torre E., and Riesgo T.: Embedded Run-time Reconfigurable Nodes for Wireless Sensor Networks Applications. IEEE Sensors Journal, Vol. 11 (9), 1800-1810 (2011).
    • (2011) IEEE Sensors Journal , vol.11 , Issue.9 , pp. 1800-1810
    • Krasteva, Y.E.1    Portilla, J.2    De La Torre, E.3    Riesgo, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.