Layout-aware optimization of STT MRAMs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1455-1458

  Gupta, Sumeet Kumar ^a   Park, Sang Phill ^a   Mojumder, Niladri Narayan ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

layout; magnetic memories; MTJ; optimization; STT MRAM; TMR

Indexed keywords

CELLS; CYTOLOGY; MAGNETIC ANISOTROPY; MAGNETIC RECORDING; MAGNETIC STORAGE; OPTIMIZATION; TRANSISTORS;

CRITICAL VALUE; LAYOUT; MAGNETIC MEMORY; NUMBER OF FINGERS; OPTIMIZATION METHODOLOGY; SPIN TRANSFER TORQUE; STT-MRAM; TRANSISTOR WIDTH;

MRAM DEVICES;

EID: 84862106053     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176595     Document Type: Conference Paper

References (9)

1. A. Raychowdhury, D. Somashekhar, T. Karnik and V. De, "Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances," IEDM, Dec. 2009.
2. N. N. Mojumder. S. K. Gupta and K. Roy, "Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations," DRC, June 2011.
3. X. Fong, S. H Choday and K. Roy, "Bit-cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching," IEEE Trans. on Nanotech, in press.
4. J. Li, P. Ndai, A. Goel, S. Salahuddin and K, Roy, "Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective," TVLSI, vol. 18, no.12, 2010.
5. N. N. Mojumder and K. Roy,"Switching current reduction and thermally induced delay spread compression in tilted magnetic anisotropy spin-transfer torque (STT) MRAM," unpublished.
6. Available: http://www.mosis.com/Technical/Designrules/scmos/
7. L. Liebman, "DfM, the teenage years," Proc of SPIE, 692502, 2008.
8. Available: http://ptm.asu.edu/
9. K. Ohe, S. Odanaka, K. Moriyama, T. Hori and G. Fuse, "Narrow-width effects of shallow trench-isolated CMOS with n+ -polysilicon gate,"IEEE Trans. Electron Devices, vol. 36, no. 6, 1989.