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Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 509-514

Static scheduling of a time-triggered network-on-chip based on SMT solving

(5) Huang, Jia a Blech, Jan Olaf a Raabe, Andreas a Buckl, Christian a Knoll, Alois b

a FORTISS GMBH (Germany)

b TECHNICAL UNIVERSITY OF MUNICH (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION ROUTE; COMPLETE PROBLEMS; DESIGN CHALLENGES; FEASIBLE SOLUTION; HIGH-THROUGHPUT; INCREMENTAL APPROACH; LOSS OF PERFORMANCE; MESSAGE SCHEDULING; MULTI PROCESSOR SYSTEMS; NETWORK ON CHIP; SATISFIABILITY MODULO THEORIES; SCHEDULING PROBLEM; STATIC SCHEDULING; TIME SLOTS; TIME TRIGGERED;

COMMUNICATION; EXHIBITIONS; HEURISTIC ALGORITHMS; SCHEDULING; SERVERS; VLSI CIRCUITS;

DESIGN;

EID: 84862081944 PISSN: 15301591 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (36)

References (10)

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2
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