-
4
-
-
84944319371
-
Symbolic model checking without BDDs
-
LNCS Springer
-
A. Biere, A. Cimatti, E.M. Clarke, and Y. Zhu Symbolic model checking without BDDs Proc. TACAS 1999 LNCS vol. 1579 1999 Springer 193 207
-
(1999)
Proc. TACAS 1999
, vol.1579
, pp. 193-207
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.M.3
Zhu, Y.4
-
7
-
-
85024721960
-
Linear encodings of bounded LTL model checking
-
5
-
A. Biere, K. Heljanko, T. Junttila, T. Latvala, and V. Schuppan Linear encodings of bounded LTL model checking Logical Methods in Computer Science 2 5:5 2006 1 64
-
(2006)
Logical Methods in Computer Science
, vol.2
, Issue.5
, pp. 1-64
-
-
Biere, A.1
Heljanko, K.2
Junttila, T.3
Latvala, T.4
Schuppan, V.5
-
9
-
-
73449144443
-
DiVinE 2.0: High-performance model checking
-
IEEE Computer Society Press
-
J. Barnat, L. Brim, and P. Ročkai DiVinE 2.0: high-performance model checking Proc. HiBi 2009 2009 IEEE Computer Society Press 31 32
-
(2009)
Proc. HiBi 2009
, pp. 31-32
-
-
Barnat, J.1
Brim, L.2
Ročkai, P.3
-
10
-
-
0000974483
-
The state explosion problem
-
LNCS Springer
-
A. Valmari The state explosion problem Lectures on Petri Nets I: Basic Models LNCS vol. 1491 1998 Springer 429 528
-
(1998)
Lectures on Petri Nets I: Basic Models
, vol.1491
, pp. 429-528
-
-
Valmari, A.1
-
11
-
-
0023452605
-
Sequential and concurrent behaviour in Petri net theory
-
E. Best, and R.R. Devillers Sequential and concurrent behaviour in Petri net theory Theoretical Computer Science 55 1 1987 87 136
-
(1987)
Theoretical Computer Science
, vol.55
, Issue.1
, pp. 87-136
-
-
Best, E.1
Devillers, R.R.2
-
12
-
-
84944063124
-
Bounded reachability checking with process semantics
-
LNCS Springer
-
K. Heljanko Bounded reachability checking with process semantics Proc. CONCUR 2001 LNCS vol. 2154 2001 Springer 218 232
-
(2001)
Proc. CONCUR 2001
, vol.2154
, pp. 218-232
-
-
Heljanko, K.1
-
13
-
-
33749564515
-
Planning as satisfiability: Parallel plans and algorithms for plan search
-
J. Rintanen, K. Heljanko, and I. Niemelä Planning as satisfiability: parallel plans and algorithms for plan search Artificial Intelligence 170 12-13 2006 1031 1080
-
(2006)
Artificial Intelligence
, vol.170
, Issue.1213
, pp. 1031-1080
-
-
Rintanen, J.1
Heljanko, K.2
Niemelä, I.3
-
14
-
-
0030352389
-
Pushing the envelope: Planning, propositional logic and stochastic search
-
AAAI Press
-
H.A. Kautz, and B. Selman Pushing the envelope: planning, propositional logic and stochastic search Proc. AAAI'96/IAAI'96, vol. 2 1996 AAAI Press 1194 1201
-
(1996)
Proc. AAAI'96/IAAI'96, Vol. 2
, pp. 1194-1201
-
-
Kautz, H.A.1
Selman, B.2
-
15
-
-
77951554394
-
SAT based bounded model checking with partial order semantics for timed automata
-
J. Esparza, R. Majumdar, Lecture Notes in Computer Science Springer
-
J. Malinowski, and P. Niebert SAT based bounded model checking with partial order semantics for timed automata J. Esparza, R. Majumdar, TACAS Lecture Notes in Computer Science vol. 6015 2010 Springer 405 419
-
(2010)
TACAS
, vol.6015
, pp. 405-419
-
-
Malinowski, J.1
Niebert, P.2
-
16
-
-
84898684063
-
Encoding planning problems in nonmonotonic logic programs
-
LNCS Springer
-
Y. Dimopoulos, B. Nebel, and J. Koehler Encoding planning problems in nonmonotonic logic programs Proc. ECP 1997 LNCS vol. 1348 1997 Springer 169 181
-
(1997)
Proc. ECP 1997
, vol.1348
, pp. 169-181
-
-
Dimopoulos, Y.1
Nebel, B.2
Koehler, J.3
-
17
-
-
38349060964
-
Planning as satisfiability with relaxed ∃-step plans
-
LNCS Springer
-
M. Wehrle, and J. Rintanen Planning as satisfiability with relaxed ∃-step plans AI 2007: Advances in Artificial Intelligence LNCS vol. 4830 2007 Springer 244 253
-
(2007)
AI 2007: Advances in Artificial Intelligence
, vol.4830
, pp. 244-253
-
-
Wehrle, M.1
Rintanen, J.2
-
18
-
-
33749552512
-
SAT-based verification of safe Petri nets
-
LNCS Springer
-
S. Ogata, T. Tsuchiya, and T. Kikuno SAT-based verification of safe Petri nets Proc. ATVA 2004 LNCS vol. 3299 2004 Springer 79 92
-
(2004)
Proc. ATVA 2004
, vol.3299
, pp. 79-92
-
-
Ogata, S.1
Tsuchiya, T.2
Kikuno, T.3
-
19
-
-
10444283520
-
BMC via dynamic atomicity analysis
-
IEEE Computer Society
-
T. Jussila BMC via dynamic atomicity analysis Proc. ACSD 2004 2004 IEEE Computer Society 197 206
-
(2004)
Proc. ACSD 2004
, pp. 197-206
-
-
Jussila, T.1
-
21
-
-
46049088418
-
-
Research Report A97, Helsinki University of Technology, Laboratory for Theoretical Computer Science, doctoral dissertation
-
T. Jussila, On bounded model checking of asynchronous systems, Research Report A97, Helsinki University of Technology, Laboratory for Theoretical Computer Science, doctoral dissertation, 2005.
-
(2005)
On Bounded Model Checking of Asynchronous Systems
-
-
Jussila, T.1
-
22
-
-
46049109150
-
Symbolic step encodings for object based communicating state machines
-
LNCS Springer
-
J. Dubrovin, T. Junttila, and K. Heljanko Symbolic step encodings for object based communicating state machines Proc. FMOODS 2008 LNCS vol. 5051 2008 Springer 96 112
-
(2008)
Proc. FMOODS 2008
, vol.5051
, pp. 96-112
-
-
Dubrovin, J.1
Junttila, T.2
Heljanko, K.3
-
23
-
-
47249124522
-
Peephole partial order reduction
-
LNCS Springer
-
C. Wang, Z. Yang, V. Kahlon, and A. Gupta Peephole partial order reduction Proc. TACAS 2008 LNCS vol. 4963 2008 Springer 382 396
-
(2008)
Proc. TACAS 2008
, vol.4963
, pp. 382-396
-
-
Wang, C.1
Yang, Z.2
Kahlon, V.3
Gupta, A.4
-
24
-
-
70350228798
-
Monotonic partial order reduction: An optimal symbolic partial order reduction technique
-
LNCS Springer
-
V. Kahlon, C. Wang, and A. Gupta Monotonic partial order reduction: an optimal symbolic partial order reduction technique Proc. CAV 2009 LNCS vol. 5643 2009 Springer 398 413
-
(2009)
Proc. CAV 2009
, vol.5643
, pp. 398-413
-
-
Kahlon, V.1
Wang, C.2
Gupta, A.3
-
25
-
-
35448932808
-
CheckFence: Checking consistency of concurrent data types on relaxed memory models
-
ACM
-
S. Burckhardt, R. Alur, and M.M.K. Martin CheckFence: checking consistency of concurrent data types on relaxed memory models Proc. PLDI 2007 2007 ACM 12 21
-
(2007)
Proc. PLDI 2007
, pp. 12-21
-
-
Burckhardt, S.1
Alur, R.2
Martin, M.M.K.3
-
26
-
-
77949385039
-
Checking bounded reachability in asynchronous systems by symbolic event tracing
-
LNCS Springer
-
J. Dubrovin Checking bounded reachability in asynchronous systems by symbolic event tracing Proc. VMCAI 2010 LNCS vol. 5944 2010 Springer 146 162
-
(2010)
Proc. VMCAI 2010
, vol.5944
, pp. 146-162
-
-
Dubrovin, J.1
-
27
-
-
33847258494
-
Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits
-
LNCS Springer
-
K.L. McMillan Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits Proc. CAV 1992 LNCS vol. 663 1993 Springer 164 177
-
(1993)
Proc. CAV 1992
, vol.663
, pp. 164-177
-
-
McMillan, K.L.1
-
30
-
-
84947440904
-
Symbolic model checking of infinite state systems using Presburger arithmetic
-
LNCS Springer
-
T. Bultan, R. Gerber, and W. Pugh Symbolic model checking of infinite state systems using Presburger arithmetic Proc. CAV 1997 LNCS vol. 1254 1997 Springer 400 411
-
(1997)
Proc. CAV 1997
, vol.1254
, pp. 400-411
-
-
Bultan, T.1
Gerber, R.2
Pugh, W.3
-
31
-
-
84947441305
-
Construction of abstract state graphs with PVS
-
LNCS Springer
-
S. Graf, and H. Saïdi Construction of abstract state graphs with PVS Proc. CAV 1997 LNCS vol. 1254 1997 Springer 72 83
-
(1997)
Proc. CAV 1997
, vol.1254
, pp. 72-83
-
-
Graf, S.1
Saïdi, H.2
-
32
-
-
0034923607
-
Symbolic model checking with rich assertional languages
-
Y. Kesten, O. Maler, M. Marcus, A. Pnueli, and E. Shahar Symbolic model checking with rich assertional languages Theoretical Computer Science 256 1-2 2001 93 112
-
(2001)
Theoretical Computer Science
, vol.256
, Issue.12
, pp. 93-112
-
-
Kesten, Y.1
Maler, O.2
Marcus, M.3
Pnueli, A.4
Shahar, E.5
-
33
-
-
35248818435
-
A logical reconstruction of reachability
-
LNCS Springer
-
T. Rybina, and A. Voronkov A logical reconstruction of reachability Proc. PSI 2003 LNCS vol. 2890 2003 Springer 222 237
-
(2003)
Proc. PSI 2003
, vol.2890
, pp. 222-237
-
-
Rybina, T.1
Voronkov, A.2
-
34
-
-
38149044860
-
Parameterized verification of infinite-state processes with global conditions
-
LNCS Springer
-
P.A. Abdulla, G. Delzanno, and A. Rezine Parameterized verification of infinite-state processes with global conditions Proc. CAV 2007 LNCS vol. 4590 2007 Springer 145 157
-
(2007)
Proc. CAV 2007
, vol.4590
, pp. 145-157
-
-
Abdulla, P.A.1
Delzanno, G.2
Rezine, A.3
-
37
-
-
38149000694
-
BEEM: Benchmarks for explicit model checkers
-
LNCS Springer
-
R. Pelánek BEEM: benchmarks for explicit model checkers Proc. SPIN 2007 LNCS vol. 4595 2007 Springer 263 267
-
(2007)
Proc. SPIN 2007
, vol.4595
, pp. 263-267
-
-
Pelánek, R.1
-
38
-
-
58049093429
-
Encoding queues in satisfiability modulo theories based bounded model checking
-
LNCS Springer
-
T. Junttila, and J. Dubrovin Encoding queues in satisfiability modulo theories based bounded model checking Proc. LPAR 2008 LNCS vol. 5330 2008 Springer 290 304
-
(2008)
Proc. LPAR 2008
, vol.5330
, pp. 290-304
-
-
Junttila, T.1
Dubrovin, J.2
-
40
-
-
70350656383
-
Boolector: An efficient SMT solver for bit-vectors and arrays
-
LNCS Springer
-
R. Brummayer, and A. Biere Boolector: an efficient SMT solver for bit-vectors and arrays TACAS LNCS vol. 5505 2009 Springer 174 177
-
(2009)
TACAS
, vol.5505
, pp. 174-177
-
-
Brummayer, R.1
Biere, A.2
-
42
-
-
0001651394
-
Minimum feedback arc sets for a directed graph
-
D.H. Younger Minimum feedback arc sets for a directed graph IEEE Transactions on Circuit Theory 10 2 1963 238 245
-
(1963)
IEEE Transactions on Circuit Theory
, vol.10
, Issue.2
, pp. 238-245
-
-
Younger, D.H.1
-
45
-
-
33745162025
-
Interpolation and SAT-based model checking
-
LNCS Springer
-
K.L. McMillan Interpolation and SAT-based model checking Proc. CAV 2003 LNCS vol. 2725 2003 Springer 1 13
-
(2003)
Proc. CAV 2003
, vol.2725
, pp. 1-13
-
-
McMillan, K.L.1
|