Capacitive-coupling wordline boosting with self-induced V CC collapse for write V MIN reduction in 22-nm 8T SRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 234-235

  Kulkarni, Jaydeep ^a   Geuskens, Bibiche ^a   Karnik, Tanay ^a   Khellah, Muhammad ^a   Tschanz, James ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

8T-CELL; ACCESS DEVICES; BITCELL; BITLINES; CELL VOLTAGES; CHARGE PUMP; CMOS TECHNOLOGY; COUPLING CAPACITANCE; EMBEDDED CHARGE; EMBEDDED MEMORY ARRAYS; FAST READ; HIGH-PERFORMANCE MICROPROCESSORS; KEEPER TRANSISTOR; LEVEL SHIFTER; POWER COSTS; PROCESS VARIATION; REGISTER FILES; SUPPLY VOLTAGES; TRADITIONAL DEVICES; VOLTAGE RANGES; WORDLINES; WRITE OPERATIONS;

CELLS; CMOS INTEGRATED CIRCUITS; CORE LEVELS; CYTOLOGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84860679245     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176990     Document Type: Conference Paper

References (4)

1. R. Kumar, et al., "A family of 45nm IA processors," ISSCC Dig. Tech. Papers, pp. 58-59, Feb 2009.
2. A. Raychowdhury et al., "PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction", ISSCC Dig. Tech. Papers, pp. 352-353, Feb. 2010.
3. CC Circuits", VLSI Circuits Symposium, pp. 48-49, June 2008.
4. M. Yuffe et al., "A fully integrated multi-CPU, GPU and memory controller 32nm processor," ISSCC Dig. Tech. Papers, pp. 264-265, Feb. 2011.