A versatile multi-modality serial link

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 332-333

  Tanaka, Yusuke ^a   Hino, Yasufumi ^a   Okada, Yasuhiro ^a   Takeda, Takahiro ^a   Ohashi, Sho ^a   Yamagishi, Hiroyuki ^a   Kawasaki, Kenichi ^a   Hajimiri, Ali ^b  

^a SONY CORPORATION   (Japan)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BAND PASS; BASE BANDS; COPPER INTERCONNECTS; DESIGN REQUIREMENTS; HIGH-SPEED LINKS; INTERFACE CIRCUITRY; MULTI-MODALITY; RE-DESIGNING; SERIAL DATA LINK; SERIAL LINK; TRANSMISSION MEDIA; TRANSMISSION MEDIUM; WIRELESS CHANNEL;

TRANSCEIVERS;

EID: 84860674036     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177034     Document Type: Conference Paper

References (6)

1. M. Chen, et al., "A 40Gb/s TX and RX Chip Set in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 146-147, Feb. 2011.
2. S. Fukuda, et al., "A 12.5+12.5Gb/s Full-Duplex Plastic Waveguide Interconnect," ISSCC Dig. Tech. Papers, pp. 150-151, Feb. 2011.
3. T. Takeya, et al., "A 12Gb/s Non-Contact Interface with Coupled Transmission Lines," ISSCC Dig. Tech. Papers, pp. 492-493, Feb. 2011.
4. John G. Proakis, Digital Communications, WCB/McGraw-Hill, 1995.
5. K. Kawasaki, et al., "A Millimeter-Wave Intra-Connect Solution," ISSCC Dig. Tech. Papers, pp. 414-415, Feb. 2010.
6. H. Hashemi and A. Hajimiri, "Concurrent Dual-Band CMOS Low Noise Amplifiers and Receiver Architectures," Symp. VLSI Circuits, pp.247-250, Jun. 2001.