A 40Gb/s TX and RX chip set in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 146-147

  Chen, Ming Shuan ^a   Shih, Yu Nan ^a   Lin, Chen Lun ^a   Hung, Hao Wei ^a   Lee, Jri ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION;

COMPLEX CIRCUITS; DELAY ELEMENTS; FEED-BACK LOOP; HIGH POWER CONSUMPTION; HIGH-SPEED TRANSCEIVERS; PARALLELIZATIONS; PERFORMANCE DEGRADATION; PVT VARIATIONS;

TRANSCEIVERS;

EID: 79955712911     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746257     Document Type: Conference Paper

References (4)

1. H. Wu, J. Tierno, P. Pepeljugoski, et al., "Differential 4-tap and 7-tap Transverse Filters in SiGe for 10Gb/s Multimode Fiber Optic Link Equalization," ISSCC Dig. Tech. Papers, pp. 180-181, Feb., 2003.
2. A. Momtaz and M. M. Green, "An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed- Forward Equalizer in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 629-639, Mar., 2010.
3. H. Sugita, K. Sunaga, K. Yamaguchi, and M. Misuno, "A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 162-163, Feb., 2010.
4. J.D.H. Alexander, "Clock Recovery from Random Binary Data," Electronics Letters, vol. 11, no. 22, pp. 541-542, Oct., 1975.