Power aware hardware prototyping of multiclass SVM classifier through reconfiguration

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2012, Pages 62-67

  Patil, Rajesh A ^a   Gupta, Gauri ^a   Sahula, Vineet ^a   Mandal, A S ^b  

^a MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^b CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE   (India)

Author keywords

Dynamic partial reconfiguration; SVM; Systolic array

Indexed keywords

COHN-KANADE DATABASE; DATA SETS; DYNAMIC PARTIAL RECONFIGURATION; EDA TOOLS; FACIAL EXPRESSION RECOGNITION; FACIAL EXPRESSIONS; FEATURE CLASSIFICATION; HARDWARE IMPLEMENTATIONS; HARDWARE PROTOTYPING; MEMORY MANAGEMENT; MULTI-CLASS SUPPORT VECTOR MACHINES; MULTICLASS SVM; PARTIAL RECONFIGURATION; POWER-AWARE; REDUCED COMPLEXITY; SVM; SYSTOLIC ARRAY ARCHITECTURE; TESTING PHASE; TRAINING AND TESTING; TRAINING PHASE; TRANSFER MECHANISMS; VECTOR MULTIPLICATION;

ARCHITECTURE; DATA TRANSFER; EMBEDDED SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GESTURE RECOGNITION; HARDWARE; SYSTOLIC ARRAYS;

SUPPORT VECTOR MACHINES;

EID: 84859920453     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2012.47     Document Type: Conference Paper

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