Half-terahertz SiGe BiCMOS technology

2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2012 - Digest of Papers

Volumn , Issue , 2012, Pages 133-136

  Rucker H ^a   Heinemann, B ^a   Fox, A ^a  

^a IHP   (Germany)

Author keywords

Heterojunction bipolar transistors; millimeter wave devices; silicon alloys; silicon bipolar BiCMOS technology

Indexed keywords

BI-CMOS; DOPING PROFILES; GATE DELAYS; HIGH-SPEED; LATERAL DEVICE; RING OSCILLATOR; SALICIDES; SIGE BICMOS TECHNOLOGY; SIGE HBTS; SILICON BIPOLAR/BICMOS TECHNOLOGY; THERMAL BUDGET;

BICMOS TECHNOLOGY; HETEROJUNCTION BIPOLAR TRANSISTORS; MILLIMETER WAVE DEVICES; MONOLITHIC INTEGRATED CIRCUITS; SILICON ALLOYS;

SEMICONDUCTING SILICON;

EID: 84858733930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SiRF.2012.6160164     Document Type: Conference Paper

References (5)

1. max of 300/500 GHz and 2.0 ps CML gate delay," in Technical Digest IEEE IEDM, 2010, pp. 688-691.
2. P. Chevalier, T. F. Meister, B. Heinemann, S. V. Huylenbroeck, W. Liebl, A. Fox, A. Sibaja-Hernandezl, and A. Chantre, "Towards THz SiGe HBTs," in Proceedings IEEE BCTM, 2011.
3. max of 240/330 GHz and gate delays below 3 ps," IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1678-1686, Sept. 2010.
4. A. Fox et al., "SiGe HBT module with 2.5 ps gate delay," in Technical Digest IEEE IEDM, 2008, pp. 731-734.
5. T. Matsumoto et al., "Novel SOI wafer engineering using low stress and high mobility CMOSFET with 〈100〉-channel for embedded RF/analog applications," in Technical Digest IEEE IEDM, 2004, pp. 663-666.