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Volumn , Issue , 2011, Pages 1948-1958

A detailed model for a high-mix low-volume ASIC fab

Author keywords

[No Author keywords available]

Indexed keywords

DATA QUALITY; DETAILED MODELS; FACTORY PERFORMANCE; MODEL GENERATION; MODELING PROCESS; MODELING TOOL; OPTIMIZATION APPROACH; SEMI-CONDUCTOR FABRICATION; VERIFICATION AND VALIDATION;

EID: 84858022387     PISSN: 08917736     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WSC.2011.6147909     Document Type: Conference Paper
Times cited : (7)

References (9)
  • 4
    • 0035705527 scopus 로고    scopus 로고
    • The Shortest Processing Time First Dispatch Rule and some Variants in Semiconductor Manufacturing
    • December. edited by B. A. Peters, J. S. Smith, D. J. Medeiros, and M. W. Rohrer, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • Rose, O. 2001, December. "The Shortest Processing Time First Dispatch Rule and some Variants in Semiconductor Manufacturing". In Proceedings of the 2001 Winter Simulation Conference, edited by B. A. Peters, J. S. Smith, D. J. Medeiros, and M. W. Rohrer, 1220-1224. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • (2001) Proceedings of the 2001 Winter Simulation Conference , pp. 1220-1224
    • Rose, O.1
  • 5
    • 0036928708 scopus 로고    scopus 로고
    • Some Issues of the Critical Ratio Dispatch Rule in Semiconductor Manufacturing
    • December. edited by E. Yücesan, C. H. Chen, J. L. Snowdon, and J. M. Charnes, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • Rose, O. 2002, December. "Some Issues of the Critical Ratio Dispatch Rule in Semiconductor Manufacturing". In Proceedings of the 2002 Winter Simulation Conference, edited by E. Yücesan, C. H. Chen, J. L. Snowdon, and J. M. Charnes, 1401-1405. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • (2002) Proceedings of the 2002 Winter Simulation Conference , pp. 1401-1405
    • Rose, O.1
  • 6
    • 1642436895 scopus 로고    scopus 로고
    • Accelerating Products under Due Date Oriented Dispatching Rules in Semiconductor Manufacturing
    • December. edited by S. Chick,P. J. Sánchez, D. Ferrin, and D. J. Morrice, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • Rose, O. 2003, December. "Accelerating Products under Due Date Oriented Dispatching Rules in Semiconductor Manufacturing". In Proceedings of the 2003 Winter Simulation Conference, edited by S. Chick,P. J. Sánchez, D. Ferrin, and D. J. Morrice, 1346-1350. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • (2003) Proceedings of the 2003 Winter Simulation Conference , pp. 1346-1350
    • Rose, O.1
  • 7
    • 17744386366 scopus 로고    scopus 로고
    • Modeling Tool Failures in Semiconductor Fab Simulation
    • December. edited by R. G. Ingalls, M. D. Rossetti, J. S. Smith, and B. A. Peters, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • Rose, O. 2004, December. "Modeling Tool Failures in Semiconductor Fab Simulation". In Proceedings of the 2004 Winter Simulation Conference, edited by R. G. Ingalls, M. D. Rossetti, J. S. Smith, and B. A. Peters, 1910 - 1914. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
    • (2004) Proceedings of the 2004 Winter Simulation Conference , pp. 1910-1914
    • Rose, O.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.