Some issues of the critical ratio dispatch rule in semiconductor manufacturing

Winter Simulation Conference Proceedings

Volumn 2, Issue , 2002, Pages 1401-1405

  Rose, Oliver ^a  

^a UNIVERSITY OF WÜRZBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; HEURISTIC METHODS; PROCESS ENGINEERING; PRODUCTION CONTROL; PRODUCTION ENGINEERING; SCHEDULING; WSI CIRCUITS;

CRITICAL RATIO (CR);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036928708     PISSN: 02750708     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Atherton, L. and R. Atherton. 1995. Wafer Fabrication: Factory Performance and Analysis. Boston: Kluwer.
2. Fowler, J. and J. Robinson. 1995. Measurement and improvement of manufacturing capacities (MIMAC): Final report. Technical Report 95062861A-TR, SEMATECH, Austin, TX.
3. Rose, O. 1998. WIP Evolution of a Semiconductor Factory after a Bottleneck Workcenter Breakdown. In Proceedings of the 1998 Winter Simulation Conference, pp. 997-1003
4. Rose, O. 2001.The Shortest Processing Time First (SPTF) Dispatch Rule and Some Variants in Semiconductor Manufacturing. In Proceedings of the 2001 Winter Simulation Conference, pp. 1220-1224.
5. Wein, L.M. 1988. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3):115-130.