Erratum: Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (IEEE Transactions on Electron Devices (2011) 58:10 (3379-3387))

IEEE Transactions on Electron Devices

Volumn 59, Issue 3, 2012, Pages 867-

  Zou, Jibin ^a   Xu, Qiumin ^a   Luo, Jieying ^a   Wang, Runsheng ^a   Huang, Ru ^a   Wang, Yangyuan ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84857642438     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2178417     Document Type: Erratum

References (1)

1. J. Zou, Q. Xu, J. Luo, R. Wang, R. Huang, and Y. Wang, "Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical Silicon nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3379-3387, Oct. 2011.