Improving the energy/power constraint for technology optimization

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Frank, D J ^a   Chang, L ^a   Haensch, W ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DESIGN GOAL; FUTURE GENERATIONS; PARALLEL DESIGN; POWER CONSTRAINTS; POWER DENSITIES; ROADMAP; TECHNOLOGY OPTIMIZATION; TECHNOLOGY SCALING; TEMPERATURE OPERATION; THREAD DESIGN;

CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRON DEVICES; LOW TEMPERATURE OPERATIONS;

OPTIMIZATION;

EID: 84857022321     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131557     Document Type: Conference Paper

References (3)

1. International Technology Roadmap for Semiconductors, 2010 update, http://www.itrs.net/
2. D. Frank, et al., IBM JRD, 50, July/Sept. 2006, p. 419.
3. C. Wann, et al., VLSI-TSA, 2005, p. 21.