Resource minimization in a real-time depth-map processing system on FPGA

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn , Issue , 2011, Pages 706-710

  Tan, Ngo Huy ^a   Hamid, Nor Hisham ^a   Sebastian, Patrick ^a   Voon, Yap Vooi ^b  

^a DEPARTMENT OF CHEMICAL ENGINEERING   (Malaysia)

^b UNIVERSITI TUNKU ABDUL RAHMAN   (Malaysia)

Author keywords

Architecture; depth map; disparity algorithm; FPGA; resource minimization

Indexed keywords

BANDWIDTH CONSTRAINT; CAMERA SYSTEMS; CLOCK CYCLES; CLOCK FREQUENCY; DEPTH-MAP; DISPARITY ALGORITHM; FRAMES PER SECONDS; HARDWARE ARCHITECTURE; LOGIC ELEMENTS; MEGA-PIXEL; MEMORY CONTROLLER; PARALLEL PROCESSING; PROCESSING SPEED; PROCESSING SYSTEMS; PROCESSOR ARCHITECTURES; RESOURCE CONSUMPTION; RESOURCE USAGE; SUM OF ABSOLUTE DIFFERENCES; WINDOW SIZE;

ALGORITHMS; ARCHITECTURE; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PIXELS;

IMAGE MATCHING;

EID: 84856861499     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TENCON.2011.6129200     Document Type: Conference Paper

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