Timing analysis of a protected operating system kernel

Proceedings - Real-Time Systems Symposium

Volumn , Issue , 2011, Pages 339-348

  Blackham, Bernard ^a   Shi, Yao ^a   Chattopadhyay, Sudipta ^b   Roychoudhury, Abhik ^b   Heiser, Gernot ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Operating system kernels; Real time systems; Software verification and validation

Indexed keywords

ADDRESS SPACE; CONTEXT-AWARE; CORRECTNESS PROOFS; DEVELOPMENT COSTS; FORMAL VERIFICATIONS; HARD REAL-TIME SYSTEMS; MEMORY PROTECTION; MICRO KERNEL; OPERATING SYSTEM KERNEL; REAL-TIME EXECUTIVES; SOFTWARE VERIFICATION AND VALIDATION; SOURCE CODES; THIRD GENERATION; TIGHT COUPLING; TIME-SHARING; TIMING ANALYSIS; UNSTRUCTURED CODES; VIRTUAL MEMORY; WORST-CASE EXECUTION TIME ANALYSIS;

CODES (SYMBOLS); INTERACTIVE COMPUTER SYSTEMS;

REAL TIME SYSTEMS;

EID: 84856547218     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2011.38     Document Type: Conference Paper

References (24)

1. F. Mehnert, M. Hohmuth, and H. Härtig, "Cost and benefit of separate address spaces in real-time operating systems," in 23rd RTSS, Austin, TX, USA, 2002.
2. G. Klein, K. Elphinstone, G. Heiser, J. Andronick, D. Cock, P. Derrin, D. Elkaduwe, K. Engelhardt, R. Kolanski, M. Norrish, T. Sewell, H. Tuch, and S. Winwood, "seL4: Formal verification of an OS kernel," in 22nd SOSP, Big Sky, MT, USA, Oct 2009, pp. 207-220.
3. J. Liedtke, "On μ-kernel construction," in 15th SOSP, Copper Mountain, CO, USA, Dec 1995, pp. 237-250.
4. X. Feng, Z. Shao, Y. Dong, and Y. Guo, "Certifying low-level programs with hardware interrupts and preemptive threads," in PLDI, Tucson, AZ, USA, Jun 2008, pp. 170-182.
5. R. Kirner, I. Wenzel, B. Rieder, and P. Puschner, "Using measurements as a complement to static worst-case execution time analysis," in Intelligent Systems at the Service of Mankind. UBooks Verlag, Dec 2005, vol. 2.
6. S. M. Petters, P. Zadarnowski, and G. Heiser, "Measurements or static analysis or both?" in 7th WS Worst-Case Execution-Time Analysis, Pisa, Italy, Jul 2007, satellite WS 19th ECRTS.
7. V. Yodaiken and M. Barabanov, "A real-time Linux," in USELINUX, Anaheim, CA, January 1997, satellite WS 1997 USENIX.
8. F. Mehnert, M. Hohmuth, S. Schönberg, and H. Härtig, "RTLinux with address spaces," in 3rd Real-Time Linux WS, Milano, Italy, Nov 2001.
9. A. Colin and I. Puaut, "Worst case execution time analysis of the RTEMS real-time operating system," in 13th ECRTS, Delft, Netherlands, Jun 13-15 2001, pp. 191-198.
10. M. Carlsson, J. Engblom, A. Ermedahl, J. Lindblad, and B. Lisper, "Worst-case execution time analysis of disable interrupt regions in a commercial real-time operating system," in 2nd Int. WS Real-Time Tools, 2002.
11. D. Sandell, A. Ermedahl, J. Gustafsson, and B. Lisper, "Static timing analysis of real-time operating system code," in 1st Int. Symp. Leveraging Applic. Formal Methods, October 2004.
12. M. Lv, N. Guan, Y. Zhang, R. Chen, Q. Deng, G. Yu, and W. Yi, "WCET analysis of the μC/OS-II real-time kernel," in 12th Int. Conf. Computational Sci. & Engin., Vancouver, Canada, Aug 2009, pp. 270-276.
13. M. Singal and S. M. Petters, "Issues in analysing L4 for its WCET," in 1st MIKES. Sydney, Australia: NICTA, Jan 2007.
14. M. Lv, N. Guan, Y. Zhang, Q. Deng, G. Yu, and J. Zhang, "A survey of WCET analysis of real-time operating systems," in ICESS, Hangzhou, China, May 2009, pp. 65-72.
15. X. Li, Y. Liang, T. Mitra, and A. Roychoudhury, "Chronos: A timing analyzer for embedded software," in Science of Computer Programming, Special issue on Experimental Software and Toolkit, vol. 69(1-3), Dec 2007.
16. J. Liedtke, "Improving IPC by kernel design," in 14th SOSP, Asheville, NC, USA, Dec 1993, pp. 175-188.
17. M. Warton, "Single kernel stack L4," BE Thesis, School Comp. Sci. & Engin., University NSW, Sydney 2052, Australia, Nov 2005.
18. G. Klein, P. Derrin, and K. Elphinstone, "Experience report: seL4 - formally verifying a high-performance microkernel," in 14th ICFP, Edinburgh, UK, Aug 2009, pp. 91-96.
19. B. Avison, "ARM Cortex-A8 instruction timings," http://www.avison.me.uk/ben/programming/cortex-a8.html, visited 8 May 2011.
20. Y.-T. Li, S. Malik, and A. Wolfe, "Efficient microarchitecture modeling and path analysis for real-time software," in 16th RTSS, 1995, pp. 298-307.
21. X. Li, A. Roychoudhury, and T. Mitra, "Modeling outof- order processors for WCET analysis," Real-Time Syst., vol. 34, pp. 195-227, 2006.
22. B. Huynh, L. Ju, and A. Roychoudhury, "Scope-aware data cache analysis for WCET estimation," in 17th RTAS, Apr 2011.
23. J. Schneider, "Why you can't analyze RTOSs without considering applications and vice versa," in 2nd WS Worst-Case Execution-Time Analysis, 2002.
24. J. Liedtke, "A high resolution MMU for the realization of huge fine-grained address spaces and user level mapping," German National Research Center for Computer Science (GMD), Sankt Augustin, Germany, Arbeitspapiere der GMD No. 791, 1993.