A new series parallel switched multilevel dc-link inverter topology

International Journal of Electrical Power and Energy Systems

Volumn 36, Issue 1, 2012, Pages 93-99

  Ramkumar, S ^a   Kamaraj, V ^b   Thamizharasan, S ^a   Jeevananthan, S ^c  

^a Surya College of Engineering and Technology   (India)

^b SSN COLLEGE OF ENGINEERING   (India)

^c PONDICHERRY ENGINEERING COLLEGE   (India)

Author keywords

Field programmable gate array (FPGA); Multilevel dc link inverter (MLDCI); Switch count; Total harmonic distortion (THD)

Indexed keywords

COMPONENT COUNT; DC-LINK; FORM LAYOUT; INVERTER TOPOLOGIES; MODULATION INDEXES; MODULATION STRATEGY; MULTILEVEL DC LINK INVERTER; MULTILEVEL INVERTER; NEW SERIES; OUTPUT VOLTAGES; PRIMARY OBJECTIVE; PULSE PATTERN; SERIES-PARALLEL; SINUSOIDAL VOLTAGE; STAIR-CASE; SUBHARMONICS; TECHNOLOGICAL INNOVATION; TOTAL HARMONIC DISTORTION (THD); VARIABLE VOLTAGE; VOLTAGE LEVELS; VOLTAGE SOURCE; WAVE FORMS;

ELECTRIC DRIVES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MATLAB; MODULATION; TOPOLOGY;

DC POWER TRANSMISSION;

EID: 84855809388     PISSN: 01420615     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.ijepes.2011.10.028     Document Type: Article

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