Evaluating the benefits of an extended memory hierarchy for parallel streamline algorithms

1st IEEE Symposium on Large-Scale Data Analysis and Visualization 2011, LDAV 2011 - Proceedings

Volumn , Issue , 2011, Pages 57-64

  Camp, David ^a   Childs, Hank ^a   Chourasia, Amit ^b   Garth, Christoph ^a   Joy, Kenneth I ^a  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Computation by Abstract Devices F.1.2 : Modes of Computation Parallelism and Concurrency; Computer Graphics I.3.3 : Picture Image Generation Display Algorithms; Programming Techniques D.1.3 : Concurrent Programming Parallel Programming

Indexed keywords

ARCHITECTURAL EVOLUTION; DATA OUTPUT; DISPLAY ALGORITHM; HARD DRIVES; I/O BANDWIDTH; I/O SUBSYSTEMS; MEMORY HIERARCHY; PRIMARY MEMORY; PROGRAMMING TECHNIQUE; SOLID STATE DRIVES; STREAMLINE COMPUTATIONS; VISUALIZATION AND ANALYSIS;

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DRIVES; HARD DISK STORAGE; PARALLEL PROGRAMMING; SUPERCOMPUTERS; VISUALIZATION;

DATA VISUALIZATION;

EID: 84055190003     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LDAV.2011.6092318     Document Type: Conference Paper

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