METRIC: Tracking down inefficiencies in the memory hierarchy via binary rewriting

International Symposium on Code Generation and Optimization, CGO 2003

Volumn , Issue , 2003, Pages 289-300

  Marathe, J ^a   Mueller, F ^a   Mohan, T ^b   De Supinski, B R ^d   McKee, S A ^c   Yoo, A ^d  

^a North Carolina State University   (United States)

^b Department of Electrical and Computer Engineering   (United States)

^c Cornell University   (United States)

^d LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

Computational modeling; Computer architecture; Contracts; Delay; Instruments; Laboratories; Large scale systems; Libraries; Manipulator dynamics; Subcontracting

Indexed keywords

BINS; COMPUTER ARCHITECTURE; CONTRACTS; INSTRUMENTS; LABORATORIES; LARGE SCALE SYSTEMS; LIBRARIES; MEMORY ARCHITECTURE; NETWORK COMPONENTS;

COMPUTATIONAL MODEL; DELAY; MANIPULATOR DYNAMICS; MEMORY PERFORMANCE; PERFORMANCE PROBLEMS; PRIMARY CONTRIBUTION; RUNNING APPLICATIONS; SUBCONTRACTING;

CACHE MEMORY;

EID: 8344285405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2003.1191553     Document Type: Conference Paper

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