Sigma: A simulator infrastructure to guide memory analysis

Proceedings of the International Conference on Supercomputing

Volumn 2002-November, Issue , 2002, Pages

  DeRose, Luiz ^a   Ekanadham, K ^a   Hollingsworth, Jeffrey K ^b   Sbaraglia, Simone ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Institute of Advanced Computer Science   (United States)

^c SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY;

ANALYSIS TOOLS; CACHE ANALYSIS; DATA COLLECTION; DATA LAYOUTS; MEMORY ANALYSIS; MEMORY REFERENCES; PERFORMANCE; PERFORMANCE VARIATIONS; PERTURBATION ANALYSIS; REFERENCE DATA;

BENCHMARKING;

EID: 84877046185     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SC.2002.10055     Document Type: Conference Paper

References (23)

1. L. DeRose and D. Reed. “SvPablo: A Multi-Language Arquiteture-Independent Performance Analysis System”. In Proceedings of the International Conference on Parallel Processing, pages 311-318, August 1999.
2. D. Reed, R. Aydt, R. Noe, P. Roth, K. Shields, B. Schwartz, and L. Tavera. “Scalable Performance Analysis: The Pablo Performance Analysis Environment”. In Proceedings of the Scalable Parallel Libraries Conference, IEEE Computer Society, 1993.
3. B. Miller, M. Callaghan, J. Cargille, J. Hollingsworth, R. Irvin, K. Karavanic, K. Kunchithapadam, and T. Newhall. “The Paradyn Parallel Performance Measurement Tools”. IEEE Computer, 28(11) pages 37-46, November 1995.
4. B. Mohr, A. Malony, and J. Cuny. “TAU Tuning and Analysis Utilities for Portable Parallel Programming”. In G. Wilson, editor, Parallel Programming using C++, M.I.T. Press, 1996.
5. J. Yan, S. Sarukkai, and P. Mehra. “Performance Measurement, Visualization and Modeling of Parallel and Distributed Programs Using the AIMS Toolkit”. Software Practice & Experience, 25(4) pages 429-461, April 1995.
6. M. Zagha, B. Larson, S. Turner and M. Itzkowitz. “Performance Analysis Using the MIPS R10000 Performance Counters”. In Proceedings of Supercomputing'96, November 1996.
7. S. Browne, J. Dongarra, N. Garner, K. London, and P. Mucci. “A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters”. In Proceedings of Supercomputing'00, November 2000.
8. R. Berrendorf, Heinz Ziegler, and Bernd Mohr. “PCL - The Performance Counter Library: A Common Interface to Access Hardware Performance Counters on Microprocessors”. Research Centre Juelich GmbH, http://www.fzjuelich.de/zam/PCL/Version 2.1, February 2002.
9. L. DeRose. “The Hardware Performance Monitor Toolkit”. In Proceedings of Euro-Par, pages 122-131, August 2001.
10. R. Sadourny. “The Dynamics of Finite-Difference Models of the Shallow-Water Equation”. In Journal of Atmospheric. Sciences, 32(4), April 1975.
11. S. Herrod. “Tango lite: A multiprocessor simulation environment”. In Stanford University, Computer Systems Laboratory, Technical report, http://citeseer.nj.nec.com/herrod93tango.html. 1993.
12. J. Veenstra and R. Fowler. “MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors”. In Proceedings of the Second International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS '94), pages 201-207, Durham, NC, January-February 1994.
13. A. Nguyen, M. Michael, A. Sharma, and J. Torrellas. “The augmint multiprocessor simulation toolkit for intel x86 architectures”. In Proceedings of the International Conference on Computer Design, 1996.
14. M. Giampapa. “Augmint6k: The Augmint multiprocessor simulation toolkit for IBM PowerPC architecture”. IBM Internal Report, 1998.
15. Intel Corporation, http://developer.intel.com/software/products/vtune/index.htm.
16. A. Agrawal, R. L. Sites, and M. Horowitz, “ATUM: A New Technique for Capturing Address Traces Using Microcode”. In Proceedings of the 13th Annual International Symposium on Computer Architecture. June 1986, pp. 119-127.
17. M. Martonosi, D. Ofelt, and M. Heinrich, “Integrating Performance Monitoring and Communication in Parallel Computers”. ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems. May 1996, Philadelphia, PA.
18. J. Kuskin, et al., “The Stanford FLASH Multiprocessor”. In Proceedings of the 21st International Symposium on Computer Architecture. April 1994, Chicago, IL, pp. 302-313.
19. B. Buck, and J. K. Hollingsworth, “Using Hardware Performance Monitors to Isolate Memory Bottlenecks”, In Proceedings of Supercomputing'02, November 2002.
20. A. J. Goldberg and J. L. Hennessy, “MTOOL: An Integrated System for Performance Debugging Shared Memory Multiprocessor Applications”. IEEE Transactions on Parallel and Distributed Systems, 1993, pp. 28-40.
21. M. Martonosi, A. Gupta, and T. Anderson, “MemSpy: Analyzing Memory System Bottlenecks in Programs”. In Proceedings of the 1992 SIGMETRICS Conference on Measurement and Modeling of Computer Systems. June 1-5, 1992, Newport, Rhode Island, pp. 1-12.
22. T. M. Chilimbi, T. Ball, S. G. Eick, and J. R. Larus, “StormWatch: A Tool for Visualizing Memory System Protocols”. In Proceedings of Supercomputing '95. December 1995, San Diego, CA.
23. S. K. Reinhardt, J. R. Larus, and D. A. Wood, “Typhoon and Tempest: User-Level Shared Memory”. In Proceedings of the ACM/IEEE International Symposium on Computer Architecture. April 1994.