Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances

IEEE Transactions on Electron Devices

Volumn 58, Issue 12, 2011, Pages 4333-4343

  Augustine, Charles ^a   Raychowdhury, Arijit ^b   Somasekhar, Dinesh ^c   Tschanz, James ^b   De, Vivek ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

Dual barrier; dual free layer; failures; magnetic memory; magnetic tunneling junction (MTJ); non equilibrium Green's function (NEGF); spin transfer torque (STT); variability; yield

Indexed keywords

DUAL-BARRIER; DUAL-FREE-LAYER; MAGNETIC MEMORIES; MAGNETIC TUNNELING JUNCTIONS; NON-EQUILIBRIUM GREEN'S FUNCTION; SPIN TRANSFER TORQUE; VARIABILITY; YIELD;

ANTIFERROMAGNETIC MATERIALS; DESIGN; ELECTRIC RESISTANCE; FAILURE (MECHANICAL); GREEN'S FUNCTION; MAGNETIC STORAGE; MEMORY ARCHITECTURE; NONVOLATILE STORAGE; SPACE RESEARCH; STATIC RANDOM ACCESS STORAGE;

MAGNETIC DEVICES;

EID: 82155166226     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2169962     Document Type: Article

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