A ROM-less direct digital frequency synthesizer based on a scaling-free CORDIC algorithm

Proceedings of the 6th International Forum on Strategic Technology, IFOST 2011

Volumn 2, Issue , 2011, Pages 1186-1189

  Cao, Yi Jiang ^a   Wang, Yang ^a   Sung, Tze Yun ^b  

^a HARBIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^b CHUNG HUA UNIVERSITY   (Taiwan)

Author keywords

DDFS; FPGA; scaling free CORDIC algorithm; SFDR

Indexed keywords

DDFS; DESIGN PROCEDURE; DIRECT DIGITAL FREQUENCY SYNTHESIZER; OPTIMIZED SOLUTIONS; ROM-LESS; SCALING-FREE CORDIC; SFDR; SPURIOUS-FREE DYNAMIC RANGE; VERILOG CODE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY SYNTHESIZERS;

ALGORITHMS;

EID: 80053409817     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IFOST.2011.6021232     Document Type: Conference Paper

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