메뉴 건너뛰기




Volumn , Issue , 2011, Pages 7096-7099

High-speed real-time signal processing system design and implementation based on FPGA

Author keywords

FFT ip core; FPGA; Sampling time; Signal gathering and processing

Indexed keywords

ACTUAL EXPERIMENTS; DIGITAL SIGNALS; HARDWARE CIRCUITS; HIGH-SPEED; HIGH-SPEED DATA; HIGH-SPEED SIGNALS; IP CORE; OPERATING PERFORMANCE; PROCESSING SPEED; REAL-TIME SIGNAL PROCESSING; SAMPLING TIME;

EID: 80053238959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AIMSEC.2011.6011079     Document Type: Conference Paper
Times cited : (3)

References (10)
  • 1
    • 80053263877 scopus 로고    scopus 로고
    • The People's Posts and Telecommunications Press, March, (in Chinese)
    • Wei Wang, Verilog HDL Programming and application. The People's Posts and Telecommunications Press, March 2005 (in Chinese).
    • (2005) Verilog HDL Programming and Application
    • Wang, W.1
  • 4
    • 80053253832 scopus 로고
    • FPGA hnplementation of FIR filters using pipelined bit-serial canonical signal Dig-it multipliers
    • Shousheng He, Mats Torkelson, "FPGA hnplementation of FIR Filters Using Pipelined Bit-serial Canonical Signal Dig-it Multipliers," IEEE Custom Integrated Circuit Conference, 1994, pp.212-215.
    • (1994) IEEE Custom Integrated Circuit Conference , pp. 212-215
    • He, S.1    Torkelson, M.2
  • 6
    • 0037332859 scopus 로고    scopus 로고
    • Performance evaluation and optimal design for fpgabased digit-serial DSP functions
    • Hanho lee, "Performance Evaluation and Optimal design for FPGAbased Digit-serial DSP Functions, " Computers and Electrical Engineering, 2003:29, 357-377.
    • (2003) Computers and Electrical Engineering , vol.29 , pp. 357-377
    • Hanho, L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.