Performance evaluation and optimal design for FPGA-based digit-serial DSP functions

Computers and Electrical Engineering

Volumn 29, Issue 2, 2003, Pages 357-377

  Lee, Hanho ^a   Sobelman, Gerald E ^b  

^a NOKIA RESEARCH CENTER   (United States)

^b University of Minnesota   (United States)

Author keywords

Adder; Arithmetic; Digit serial; Digital signal processing; Field programmable gate array; FIR filter; Multiplier

Indexed keywords

ADDERS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; FIR FILTERS;

LOGIC MODULES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0037332859     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0045-7906(01)00043-X     Document Type: Article

References (22)

1. Isshiki T., Dai W.W. High-level bit-serial datapath synthesis for multi-FPGA systems. Proceeding of ACM Third International Symposium on Field Programmable Gate Arrays, 1995. p. 167-73.
2. He S., Torkelson M. FPGA implementation of FIR filters using pipelined bit-serial canonical signed digit multipliers. Proceedings of IEEE 1994 Custom Integrated Circuits Conference, 1994. p. 81-4.
3. Panneerselvam G., Graumann P.J.W., Turner L.E. Implementation of fast fourier transforms and discrete cosine transforms in FPGAs. 5th International Workshop on Field-Programmable Logic and Applications (FPL'95), 1995. p. 272-81.
4. Turner L.E., Graumann P.J.W., Gibb S.G. Bit-serial FIR filters with CSD coefficients for FPGAs. 5th International Workshop on Field-Programmable Logic and Applications (FPL'95), 1995. p. 311-20.
5. Hartley R.I., Corbett P. Digit-serial processing techniques. IEEE Trans Circ Syst. 37:1990;707-719.
6. Parhi K.K. A systematic approach for design of digit-serial signal processing architectures. IEEE Trans Circ Syst. 38:1991;358-375.
7. Parhi K.K., Wang C.Y., Brown A.P. Synthesis of control circuits in folded pipelined DSP architectures. IEEE J Solid-State Circ. 27:1992;29-43.
8. Hartley R.I., Parhi K.K. Digit-serial computation. 1995;Kluwer, Boston, MA.
9. Aggoun A., Ibrahim M.K., Ashur A. Bit-level pipelined digit-serial array processors. IEEE Trans Circ Syst. 45(7):1998;857-868.
10. Chang Y.N., Satyanarayana J.H., Parhi K.K. Systematic design of high-speed and low-power digit-serial multipliers. IEEE Trans Circ Syst II - Analog Dig Signal Process. 45(12):1998;1585-1596.
11. Chang Y.N., Parhi K.K. High-performance digit-serial complex-number multiplier-accumulator. Proceedings of 1998 IEEE International Conference on Computer Design, October 1998. p. 211-13.
12. Suzuki H., Chang Y.N., Parhi K.K. Performance tradeoffs in digit-serial DSP systems. Proceedings of 1998 Asilomar Conference on Signals, Systems and Computers, vol. 2, November 1998. p. 1225-9.
13. Lee H., Sobelman G.E. FPGA-based FIR filters using digit-serial arithmetic. Proceedings of IEEE International ASIC Conference, September 1997. p. 225-8.
14. Lee H., Sobelman G.E. Digit-serial DSP library for optimized FPGA configuration. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 1998. p. 322-23.
15. Lee H., Chung J., Sobelman G.E. FPGA-based digit-serial CSD FIR filter for image signal format conversion. Proceedings of International Conference On Signal Processing Applications and Technology, September 1998.
16. Valls J., Peiro M.M., Sansaloni T., Boemo E. A study about FPGA-based digital filters. 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation, 1998. p. 192-201.
17. Valls J., Sansaloni T., Peiro M.M., Boemo E. Fast FPGA-based pipelined digit-serial/parallel multipliers. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, vol. 1, 1999. p. 482-5.
18. Albaharna O.T., Cheung P.Y.K., Clarke T.J. Area and time limitations of FPGA-based virtual hardware. Proceedings of the IEEE International Conference on Computer Design, October 1994. p. 184-9.
19. Albaharna O.T., Cheung P.Y.K., Clarke T.J. On the viability of FPGA-based integrated coprocessors. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 1996. p. 206-15.
20. Xing S., Yu W.W.H. FPGA adders: performance evaluation and optimal design. IEEE Des Test Comput 1998:24-29.
21. Xilinx. The Programmable Logic Data Book, Xilinx Inc., 1998.
22. Xilinx. XACT LIBRARIES, Xilinx Inc., 1996.