RCKMPI - Lightweight MPI implementation for intel's single-chip cloud computer (SCC)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6960 LNCS, Issue , 2011, Pages 208-217

  Comprés Ureña, Isaías A ^a   Riepen, Michael ^a   Konow, Michael ^a  

^a Microprocessor and Programming Research Labs (MPR)   (Germany)

Author keywords

Many Core Processors; Message Passing; MPI; RCKMPI

Indexed keywords

DISTRIBUTED MEMORY ARCHITECTURE; LOW LEVEL; MPI; PROTOCOL OVERHEAD; RCKMPI; RUNTIMES; SHARED MEMORIES; SINGLE-CHIP; SMALL SIZE; MANY-CORE PROCESSORS; MPI IMPLEMENTATIONS; SHARED MEMORY; SINGLE-CHIP CLOUD COMPUTERS;

CLOUD COMPUTING; MEMORY ARCHITECTURE;

MESSAGE PASSING;

EID: 80053027876     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-24449-0_24     Document Type: Conference Paper

References (10)

1. Mattson, T.G., Van der Wijngaart, R.F., Riepen, M., et al.: The 48-core SCC processor: the programmer's view. In: Proceedings of the 2010 ACM/IEEE Conference on Supercomputing, SC 2010, New Orleans, Louisiana (November 2010)
2. Clauss, C., Lankes, S., Galowicz, J. Bemmerl, T.: iRCCE: A Non-blocking Communication Extension to the RCCE Communication Library for the Intel Single-Chip Cloud Computer, Chair for Operating Systems, RWTH Aachen University, December 17 (2010)
3. van der Wijngaart, R.F., Mattson, T.G., Haas, W.: Light-weight Communications on Intel's Single-Chip Cloud Computer Processor
4. Howard, J., Dighe, S., Hoskote, Y., et al.: A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS. In: Proceedings of the International Solid-State Circuits Conference (February 2010)
5. Buntinas, D., Mercier, G., Gropp, W.: Implementation and Shared-Memory Evaluation of MPICH2 over the Nemesis Communication Subsystem. Mathematics and Computer Science Division, Argonne National Laboratory
6. Argonne National Laboratory: MPICH2, http://www.mcs.anl.gov/mpi/mpich2
7. Thakur, R., Rabenseifner, R., Gropp, W.: Optimization of Collective Communication Operations in MPICH. International Journal of High Performance Computing Applications (Spring 2005)
8. Thakur, R., Gropp, W.D.: Improving the performance of collective operations in MPICH. In: Dongarra, J., Laforenza, D., Orlando, S. (eds.) EuroPVM/MPI 2003. LNCS, vol. 2840, pp. 257-267. Springer, Heidelberg (2003)
9. Hensgen, D., Finkel, R., Manber, U.: Two algorithms for barrier synchronization. International Journal of Parallel Programming (1988)
10. NASA Advanced Supercomputing Division Parallel Benchmarks, http://www.nas.nasa.gov/Resources/Software/npb.html