-
1
-
-
61849177075
-
Optimal spatial resolution of epidural and subdural electrode arrays for brain-machine interface applications
-
M. W. Slutzky, L. R. Jordan, and L. E. Miller, "Optimal spatial resolution of epidural and subdural electrode arrays for brain-machine interface applications," in Engineering in Medicine and Biology Society, 2008. EMBS 2008. 30th Annual International Conference of the IEEE, 2008, pp. 3771-3774.
-
Engineering in Medicine and Biology Society, 2008. EMBS 2008. 30th Annual International Conference of the IEEE, 2008
, pp. 3771-3774
-
-
Slutzky, M.W.1
Jordan, L.R.2
Miller, L.E.3
-
2
-
-
84870445275
-
Quantifying auditory event-related responses in multichannel human intracranial recordings
-
2010-March-19
-
D. Boatman-Reich, P. J. Franaszczuk, A. Korzeniewska, B. Caffo, E. K. Ritzl, et al., "Quantifying auditory event-related responses in multichannel human intracranial recordings," Frontiers in Computational Neuroscience, vol. 4, p. 12, 2010-March-19 2010.
-
(2010)
Frontiers in Computational Neuroscience
, vol.4
, pp. 12
-
-
Boatman-Reich, D.1
Franaszczuk, P.J.2
Korzeniewska, A.3
Caffo, B.4
Ritzl, E.K.5
-
3
-
-
33846258717
-
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System
-
R. Harrison, P. Watkins, R. Kier, R. Lovejoy, D. Black, et al., "A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System," Solid-State Circuits, IEEE Journal of, vol. 42, p. 123, 2007.
-
(2007)
Solid-State Circuits, IEEE Journal of
, vol.42
, pp. 123
-
-
Harrison, R.1
Watkins, P.2
Kier, R.3
Lovejoy, R.4
Black, D.5
-
4
-
-
77952182738
-
An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications
-
S. B. Lee, H.-M. Lee, M. Kiani, U.-M. Jow, and M. Ghovanloo, "An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 120-121.
-
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010
, pp. 120-121
-
-
Lee, S.B.1
Lee, H.-M.2
Kiani, M.3
Jow, U.-M.4
Ghovanloo, M.5
-
6
-
-
67651148236
-
A 300 nW, 15 ppm/°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
-
K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, "A 300 nW, 15 ppm/°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs," Solid-State Circuits, IEEE Journal of, vol. 44, pp. 2047-2054, 2009.
-
(2009)
Solid-State Circuits, IEEE Journal of
, vol.44
, pp. 2047-2054
-
-
Ueno, K.1
Hirose, T.2
Asai, T.3
Amemiya, Y.4
-
7
-
-
14644436467
-
A 2-nW 1.1-V self-biased current reference in CMOS technology
-
DOI 10.1109/TCSII.2004.842059
-
E. Camacho-Galeano, C. Galup-Montoro, and M. Schneider, "A 2-nW 1.1-V self-biased current reference in CMOS technology," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, pp. 61-65, 2005. (Pubitemid 40319478)
-
(2005)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.52
, Issue.2
, pp. 61-65
-
-
Camacho-Galeano, E.M.1
Galup-Montoro, C.2
Schneider, M.C.3
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