New security threats against chips containing scan chain structures

2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011

Volumn , Issue , 2011, Pages 105-110

  Da Rolt, Jean ^a   Di Natale, Giorgio ^a   Flottes, Marie Lise ^a   Rouzeyre, Bruno ^a  

^a LIRMM   (France)

Author keywords

scan based attack; security; testability

Indexed keywords

CRYPTOGRAPHIC FUNCTIONS; INDUSTRIAL TESTS; LARGE DESIGNS; SCAN ATTACK; SCAN CHAIN; SCAN-BASED ATTACK; SECRET INFORMATION; SECURITY; SECURITY THREATS; SEQUENTIAL ELEMENTS; SINGLE SCAN; SPATIAL RESPONSE; TEST COST; TEST INFRASTRUCTURES; TEST-RESPONSE COMPACTION; TESTABILITY;

COMPACTION;

INTEGRATED CIRCUIT TESTING;

EID: 80052010257     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HST.2011.5955005     Document Type: Conference Paper

References (18)

1. Bo Y.; Kaijie W.; Karri R., "Secure Scan: A Design-for-Test Architecture for Crypto Chips", IEEE Transactions on CAD, vol.25, no.10, pp. 2287-2293, Oct. 2006
2. Bo Y.; Kaijie W.; Karri R.; "Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard," Proc. ITC 2004, pp. 339-344.
3. Hély D., Bancel F., Flottes M.-L., Rouzeyre B. "Securing Scan Control in Crypto Chips". J. Electron. Test. 23, 5 (October 2007), pp. 457-464 (Pubitemid 350050702)
4. Hély D.et al., "Scan Pattern Watermarking", LATW 2006
5. Lee J., Tebranipoor M., Plusquellic, J. "A low-cost solution for protecting IPs against scan-based side-channel attacks," Proc. VTS 2006, pp.93-99
6. Paul S., Chakraborty R. S., Bhunia, S., "VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips," Proc VTS 2007. pp.455-460.
7. Hely D., Bancel F.; Flottes M. L., Rouzeyre, B., "Test control for secure scan designs," Proc. ETS 2005, pp. 190-195.
8. Hély D., "Testability of Secure ICs", PhD report University of Montpellier 2, 2005
9. Mukhopadhyay D., Banerjee S., RoyChowdhury D.; Bhattacharya, B. B.;, "CryptoScan: A Secured Scan Chain Architecture", Proc. 14th ATS 2005, pp. 348-353.
10. Hely D., Flottes M.-L., Bancel, F., Rouzeyre B., Berard, N., Renovell M., "Scan design and secure chip [secure IC testing]," Proc. IOLTS 2004. pp. 219-224.
11. Lee, J.; Tehranipoor, M.; Patel, C.; Plusquellic, J.; "Securing Designs against Scan-Based Side-Channel Attacks," IEEE Trans. on Dependableand Secure Computing, vol.4, no.4, pp.325-336.
12. Sengar G., Mukhopadhyay D., Chowdhury D. R., "Secured Flipped Scan-Chain Model for Crypto-Architecture," IEEE Trans. on CAD, vol. 26, no.11, pp.2080-2084, Nov. 2007
13. Elm M., Wunderlich H.-J.; "Scan Chain Organization for Embedded Diagnosis", Proc. DATE 2008, pp.468-473.
14. Vranken H., Kumar Goel S., Glowatz A., Schloeffel J., Hapke, F.; "Fault detection and diagnosis with parity trees for space compaction of test responses", Proc. DAC 2006, pp.1095-1098.
15. Liu C., Huang Y.; "Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance," Proc. VTS, 2007. pp. 461-468.
16. http://csrc.nist.gov/publications/PubsFIPS.html
17. J. Rajski, et al., Embedded Deterministic Test for Low Cost Manufacturing Test. Proc. Int. Test Conf., pp. 301-310, 2002. (Pubitemid 35411432)
18. S. Mitra and K. S. Kim, X-Compact: An Efficient Response Compaction Technique. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 421-432, 2004