A low-power implantable neuroprocessor on nano-FPGA for Brain Machine interface applications

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn , Issue , 2011, Pages 1593-1596

  Zhang, Fei ^a   Aghagolzadeh, Mehdi ^a   Oweiss, Karim ^a,b  

^a Michigan State University   (United States)

^b MICHIGAN STATE UNIVERSITY   (United States)

Author keywords

brain machine interfaces; compression; low power; nano FPGA; Neuroprocessor; spike sorting

Indexed keywords

BRAIN MACHINE INTERFACE; LOW POWER; NANO-FPGA; NEUROPROCESSOR; SPIKE-SORTING;

DATA REDUCTION; SIGNAL PROCESSING; SPEECH COMMUNICATION;

SORTING;

EID: 80051662522     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2011.5946801     Document Type: Conference Paper

References (15)

1. M. A. Lebedev and M. A. L. Nicolelis, "Brain-Machine Interfaces: Past, Present and Future," Trends Neurosci., vol. 29, pp. 536-546, 2006.
2. D. M. Taylor, S. I. H. Tillery, and A. B. Schwartz, "Direct Cortical Control of 3D Neuroprosthetic Devices," Science, vol. 296, pp. 1829-1832, 2002.
3. K. G. Oweiss, "A Systems Approach for Data Compression and Latency Reduction in Cortically Controlled Brain Machine Interfaces", IEEE Trans. BE, vol. 53, pp. 1364-1377, 2006
4. H. Miranda, V. Gilja, C. A. Chestek, K. V. Shenoy, and T. H. Meng, "HermesD: A High-rate Long-range Wireless Transmission System for Simultaneous Multichannel Neural Recording Applications," IEEE Trans. BioCAS, vol. 4, pp. 181-191, 2010.
5. Y. K. Song, D. A. Borton, S. Park, W. R. Patterson, and C. W. Bull et al "Active Microelectronic Neurosensor Arrays for Implantable Brain Communication Interfaces," IEEE Trans. NSRE, vol. 17, pp. 339-345, 2009.
6. R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black, B. Greger, and F. Solzbacher, "A Low-power Integrated Circuit for a Wireless 100-electrode Neural Recording System," IEEE J. Solid-State Circuits, vol. 42, pp. 123-133, 2007.
7. A. M. Sodagar, G. E. Perlin, Y. Ying, K. Najafi, and K. D. Wise, "An Implantable 64-channel Wireless Microsystem for Single-unit Neural Recording," IEEE J. Solid-State Circuits, vol. 44, pp. 2591-2604, 2009.
8. R. Michael, I. Obeid, S. H. Callender and P. D. Wolf, "A Single-chip Signal Processing and Telemetry Engine for an Implantable 96-channel Neural Data Acquisition System," J. Neural Eng., vol. 4, pp. 309, 2007.
9. Y. Perelman and R. Ginosar, "An Integrated System for Multichannel Neuronal Recording with Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection," IEEE Trans. BE, vol. 54, pp. 130-137, 2007.
10. M. S. Chae, Z. Yang, M. R. Yuce, H. Linh, and W. Liu, "A 128-channel 6 mW Wireless Neural Recording IC with Spike Feature Extraction and UWB Transmitter," IEEE Trans. NSRE, vol. 17, pp. 312-321, 2009.
11. F. Zhang, M. Aghagolzadeh, M. Kiani, M. Ghovanloo, K. G. Oweiss, "WIMNIS 1.0: Wireless Intracortical Multichannel Neural Interface System for Neural Recording in Freely Behaving Subjects," in preparation.
12. M. Aghagolzadeh and K. G. Oweiss, "Compressed and Distributed Sensing of Neuronal Activity for Real Time Spike Train Decoding," IEEE Trans. NSRE, vol. 17, pp. 116-127, 2009.
13. K. G. Oweiss, A. Mason, Y. Suhail, A. M. Kamboh, and K. E. Thomson, "A Scalable Wavelet Transform VLSI Architecture for Real-time Signal Processing in High-density Intra-cortical Implants," IEEE Trans. CAS I, vol. 54, pp. 1266-1278, 2007.
14. http://www.actel.com/documents/IGLOO-nano-DS.pdf.
15. K. G. Oweiss, Statistical Signal Processing for Neuroscience and Neurotechnology, Academic Press, Elsevier, pp. 15-74, 2010.