A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 825-828

  Salem, Loai G ^a   Jain, Rinkle ^b  

^a NILE UNIVERSITY   (Egypt)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; CONTROL LOOP; CONTROL TECHNIQUES; CYCLE BASIS; LOAD CURRENTS; MITIGATION TECHNIQUES; OUTPUT VOLTAGE RIPPLE; SWITCHED CAPACITOR; SWITCHED-CAPACITOR DC-DC CONVERTER;

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; VOLTAGE REGULATORS;

DC-DC CONVERTERS;

EID: 79960849626     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5937693     Document Type: Conference Paper

References (8)

1. D. D. Buss, "Technology in the Internet Age," IEEE International Solid-State Circuits Conference, 2002.
2. T. V. Breussegem and M. Steyaert, "A 82% efficiency 0.5% ripple 16- phase fully integrated capacitive voltage doubler," IEEE Symp. VLSI Circuits, pp. 198-199, Jun. 2009.
3. Hanh-Phuc Le, et al., "A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiecny," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010.
4. D. Somasekhar, et al., "Multi-phase 1GHz voltage doubler chargepump in 32nm logic process," IEEE Symp. VLSI Circuits, pp. 196-197, Jun. 2009.
5. Y. Ramadass, A. Fayed, B. Haroun, and A. Chandrakasan, "A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010.
6. Hoi Lee and Philip k. T. Mok, "An SC voltage doubler with pseudocontinuous output regulation using a three-stage switchable Opamp," IEEE J. of Solid-State Circuits, vol. 42, no. 6, pp. 1216-1229, June 2007.
7. M. Seeman, "A design methodology for switched-capacitor DC-DC converters," Ph.D. dissertation, University of California at Berkeley, May 2009.
8. A. J. López-Martín, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, "Low-voltage super class AB CMOS OTA cells with very high slew rate and power efficiency," IEEE J. Solid-State Circuits, Vol. 40, No. 5, pp. 1068-1077, May 2005.