Multi-phase 1GHz voltage doubler charge-pump in 32nm logic process

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 196-197

  Somasekhar, Dinesh ^a   Srinivasan, Balaji ^a   Pandya, Gunjan ^a   Hamzaoglu, Fatih ^a   Khellah, Muhammad ^a   Karnik, Tanay ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE-PUMP; CLOSE PROXIMITY; DIGITAL LOGIC; DOUBLERS; LOGIC BLOCKS; LOGIC PROCESS; LOW CURRENTS; OUTPUT TRANSITION; PHASE 1; POWER DELIVERY; STORAGE RESERVOIRS; VOLTAGE BOOST; VOLTAGE DOUBLER;

CAPACITANCE; CAPACITORS; ELECTRIC POWER TRANSMISSION; PUMPS;

VLSI CIRCUITS;

EID: 70449553867     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. 2 SRAM in a 291Mb Array," IEDM 2008.
2. John F. Dickson, "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE Journal of Solid-State Circuits, vol. SC-11, no. 3, Jun 1976, pp. 374-378.
3. Pierre Favrat, et.al., "A High-Efficiency CMOS Voltage Doubler," IEEE Journal of Solid-State Circuits, vol.33, no. 3, Mar 1998, pp. 410-416.
4. K. Phang and D. Johns, "A 1V 1mW CMOS Front-End with On-chip Dynamic Gate Biasing for a 75Mb/s Optical Receiver," IEEE Int. Solid-State Circ. Conf., Feb 2001, pp. 218-219.