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Volumn 11, Issue 2, 2011, Pages 121-129
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A high performance co-design of 26 nm 64 Gb MLC NAND flash memory using the dedicated NAND flash controller
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Author keywords
Controller; Cycling; Disturbance; Interference; Moving read; NAND FLASH memory; ONFI; Randomization; Retention; SiP; SoC; Virtual negative read
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Indexed keywords
CYCLING;
DISTURBANCE;
MOVING READ;
NAND FLASH MEMORY;
ONFI;
RANDOMIZATION;
RETENTION;
SIP;
SOC;
VIRTUAL NEGATIVE READ;
CONTROLLERS;
MOBILE DEVICES;
NAND CIRCUITS;
FLASH MEMORY;
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EID: 79960263957
PISSN: 15981657
EISSN: None
Source Type: Journal
DOI: 10.5573/JSTS.2011.11.2.121 Document Type: Article |
Times cited : (13)
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References (3)
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