HeteroScouts: Hardware assist for OS scheduling in heterogeneous CMPs

Performance Evaluation Review

Volumn 39, Issue 1 SPEC. ISSUE, 2011, Pages 149-150

  Srinivasan, Sadagopan ^a   Iyer, Ravishankar ^a   Zhao, Li ^a   Illikkal, Ramesh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CMPs; Heterogeneous architectures; OS scheduling; Performance

Indexed keywords

SCHEDULING;

CHIP MULTIPROCESSOR; CORE COMPLEX; HARDWARE ASSIST; HETEROGENEOUS ARCHITECTURES; HETEROGENEOUS CHIP MULTIPROCESSOR; OPERATING SYSTEM SCHEDULING; OUT OF ORDER; PERFORMANCE; SUPERSCALAR; SYSTEM SCHEDULING;

PIPELINES;

EID: 79960169335     PISSN: 01635999     EISSN: None     Source Type: Journal    
DOI: 10.1145/1993744.1993800     Document Type: Conference Paper

References (4)

1. R. Kumar, et al. "Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction". In Proceedings of the 36th International Symposium on Microarchitecture.
2. T. Li, et al. Operating System Support for Overlapping-ISA Heterogeneous Multi-core Architectures. In Proceedings of High Performance Computer Architecture, 2010.
3. M. Becchi and P. Crowley. Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures. In Computing Frontiers, 2006.
4. S. Eyerman, et al. A Performance Counter Architecture for Computing Accurate CPI Components. In Proceedings of Architectural Support for Programming Languages and Operating Systems, 2006.