Parallelization of binary and real-coded genetic algorithms on GPU using CUDA

2010 IEEE World Congress on Computational Intelligence, WCCI 2010 - 2010 IEEE Congress on Evolutionary Computation, CEC 2010

Volumn , Issue , 2010, Pages

  Arora, Ramnik ^a   Tulshyan, Rupesh ^a   Deb, Kalyanmoy ^a,b  

^a INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^b Kanpur Genetic Algorithms Laboratory   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CODE OPTIMIZATION; CONSTRAINT VIOLATION; HYBRID MODEL; MASTER-SLAVE; NUMBER OF THREADS; PARALLEL GA; PARALLELIZATIONS; POPULATION SIZES; PROBLEM SIZE; REAL-CODED GENETIC ALGORITHM; SEQUENTIAL ALGORITHM; SPEED-UPS;

ARTIFICIAL INTELLIGENCE; PARALLEL ARCHITECTURES; POPULATION STATISTICS;

GENETIC ALGORITHMS;

EID: 79959453403     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CEC.2010.5586260     Document Type: Conference Paper

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