Stack distance based worst-case instruction cache performance analysis

Proceedings of the ACM Symposium on Applied Computing

Volumn , Issue , 2011, Pages 723-728

  Liu, Yu ^a   Zhang, Wei ^b  

^a Southern Illinois University at Carbondale   (United States)

^b Virginia Commonwealth University   (United States)

Author keywords

instruction caches; stack distance; static timing analysis; worst case execution time

Indexed keywords

DISTANCE-BASED; HARD REAL-TIME SYSTEMS; INSTRUCTION CACHE MISS; INSTRUCTION CACHES; MODERN MICROPROCESSOR; OUT-OF-ORDER EXECUTION; PERFORMANCE ACCELERATION; SCHEDULABILITY; STACK DISTANCE; STATIC TIMING ANALYSIS; TIMING ANALYSIS; WORST-CASE EXECUTION TIME; WORST-CASE EXECUTION TIME ANALYSIS;

EMBEDDED SYSTEMS; REAL TIME SYSTEMS;

CACHE MEMORY;

EID: 79959324326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1982185.1982343     Document Type: Conference Paper

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