Using an FPGA to accelerate pupil isolation in iris recognition

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2010, Pages 1774-1777

  Shafer, Jennifer L ^a   Ngo, Hau ^a   Ives, Robert W ^a  

^a UNITED STATES NAVAL ACADEMY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEPARTMENT OF DEFENSE; DEPARTMENT OF HOMELAND SECURITY; HARDWARE DESIGN; IRIS RECOGNITION; IRIS RECOGNITION ALGORITHM; SPEED-UPS;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

BIOMETRICS;

EID: 79957993875     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2010.5757846     Document Type: Conference Paper

References (5)

1. J. Daugman, "Probing the uniqueness and randomness of IrisCodes: Results from 200 billion iris pair comparisons." Proceedings of the IEEE, vol. 94, no. 11, pp 1927-1935.
2. nd Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov. 2008.
3. John Canny, "A Computational Approach to Edge Detection," IEEE Transactions of Pattern Analysis and Machine Intelligence, vol. PAMI-8, no. 6, pp 679-698.
4. nd Annual Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, Nov. 2008.
5. Altera, "TriMatrix Embedded Memory Blocks in Stratix IV Devices," Altera Corporation Stratix IV Device Handbook, vol 1, March 2010.