Drain current model for single electron transistor operating at high temperature

International Multi-Conference on Systems, Signals and Devices, SSD'11 - Summary Proceedings

Volumn , Issue , 2011, Pages

  Krout, I ^a   Touati, M A ^a   Boubaker, A ^a   Sghaier, N ^a   Kalboussi, A ^a  

^a FACULTÉ DES SCIENCES DE MONASTIR   (Tunisia)

Author keywords

Device modeling; high temperature; Single electron transistor; Thermionic effect; Tunneling effect

Indexed keywords

DEVICE MODELING; HIGH TEMPERATURE; SINGLE ELECTRON; THERMIONIC EFFECTS; TUNNELING EFFECT;

CAPACITANCE MEASUREMENT; CMOS INTEGRATED CIRCUITS; DRAIN CURRENT; ELECTRON TRAPS; TRANSIENTS;

SINGLE ELECTRON TRANSISTORS;

EID: 79957887654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSD.2011.5767423     Document Type: Conference Paper

References (13)

1. C. Wasshuber, "Computational Electronics". New York: Springer Verlag, 2002.
2. Chen, R. H., A. N. Korotkov, and K. K. Likharev, "A New Logic Family Based on Single-Electron Transistors", in Proc. Device Research Conference, pp. 44-45. 1995
3. Yu, Y., et al., "Implementation of Single Electron Circuit Simulation by SPICE: KOSECSPICE", in Proc. Asia Pacific Workshop on Fundamental and Application of Advanced Semiconductor Device" pp. 85-90. 2000.
4. Fonseca, L. R. C., A. N. Korotkov, and K. Likharev, "A Numerical Study of the Dynamics and Statistics of Single Electron Systems", Journal of applied physics vol. 78, No. 5, 1995, pp. 3238-3251.
5. K. Likharev, "SETTRANS-A Simulator for Single Electron transistor", http://hana.physics.sunysb.edu/set/software.
6. S. Mahapatra and A. M. Inoscu "Hybrid CMOS Single-Electron- Transistor Device and Circuit Design", ARTECH HOUSE, INC. 2006.
7. J. C. Ranuarez, M. J. Deen and C. H. Chen "A review of gate tunneling current in MOS devices". Microelectronics and reliability vol 46(12). Pp 1939-1956, 2006. (Pubitemid 44436281)
8. 2". Journal of applied physics vol 40, no. 1. pp 278-283. 1969.
9. M. Hocevar, "Croissance et caractérisation électrique de nanocristaux de InAs/SiO2 pour des applications mémoires non volatiles sur silicium", Oct. 2008.
10. A. Boubaker, "Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature". Journal of Semiconductor technology and science, vol. 10, NO.2 Jun. 2010.
11. nd ed. New York: Wiley; 1981 pp. 254.
12. C. Dubuc, J. Beauvais, and D. Drouin, "A Nanodamascene Process for Advanced Single-Electron Transistor Fabrication", IEEE transactions on nanotechnology", vol. 7, no. 1, pp 68-73, Jan. 2008.
13. C. Dubuc, A. Beaumont, J. Beauvais, and D. Drouin, "Current conduction models in the high temperature singleelectron transistor", Solid-State Electronics, vol 53, pp 478-482 April. 2009.