On-chip cache hierarchy-aware tile scheduling for multicore machines

Proceedings - International Symposium on Code Generation and Optimization, CGO 2011

Volumn , Issue , 2011, Pages 161-170

  Liu, Jun ^a   Zhang, Yuanrui ^a   Ding, Wei ^a   Kandemir, Mahmut ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALTERNATE METHOD; APPLICATION PROGRAMS; CACHE MISS; COMPUTATION KERNEL; DATA REUSE; EMBEDDED APPLICATION; EXECUTION TIME; INTEL MACHINES; ITERATION SPACES; KEY COMPONENT; MULTI-CORE MACHINES; MULTI-PROCESSOR PLATFORMS; MULTITHREADED CODE GENERATION; ON-CHIP CACHE; PARALLELIZATIONS; SCHEDULING STRATEGIES; SOURCE-TO-SOURCE TRANSLATIONS; UNIPROCESSORS;

AUTOMATIC PROGRAMMING; NETWORK COMPONENTS; OPTIMIZATION; SCHEDULING ALGORITHMS;

MULTITASKING;

EID: 79957454903     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CGO.2011.5764684     Document Type: Conference Paper

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