An analytical model for loop tiling and its solution

2000 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2000

Volumn , Issue , 2000, Pages 146-153

  Sarkar, V ^a   Megiddo, N ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM ALMADEN RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODELS; COMPUTER ARCHITECTURE; ITERATIVE METHODS; MEMORY ARCHITECTURE; PROGRAM COMPILERS;

CONSTANT TIME ALGORITHMS; MEMORY HIERARCHY; OPTIMAL SOLUTIONS; OPTIMIZING COMPILERS; PROCESSOR DESIGNERS; PRODUCTION QUALITY; PROGRAM TRANSFORMATIONS; RATIONAL POLYNOMIAL;

CACHE MEMORY;

EID: 33748307622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2000.842294     Document Type: Conference Paper

References (12)

1. S. G. Abraham and D. E. Hudak. Compile-time partitioning of iterative parallel loops to reduce cache coherency traffic, IEEE Transactions on Parallel and Distributed Systems, 2(3):318-328, July 1991.
2. Stephanie Coleman and Kathryn McKinley. Tile size selection using cache organization and data layout. In SIGPLAN '95 Conference on Programming Language Design and Implementation, pages 279-290, June 1995. SIGPLAN Notices, 30(6).
3. Jeanne Ferrante, Vivek Sarkar, and Wendy Thrash. On Estimating and Enhancing Cache Effectiveness. Lecture Notes in Computer Science, (589):328-343, 1991. Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing, Santa Clara, California, USA, August 1991, Edited by U. Banerjee, D. Gelernter, A. Nicolau, D. Padua.
4. Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. 1997 International Conference on Supercomputing, pages 317-324, 1997.
5. Monica S. Lam, Edward E. Rothberg, and Michael E. Wolf, The Cache Performance and Optimization of Blocked Algorithms. Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, April 1991.
6. Hrabri Rajic and Sanjiv Shah. Maximum Performance Code Restructuring for Hierarchical Memory RISC Computers. SIAM Conference, Houston, Texas, March 1991.
7. J. Ramanujam and P. Sadayappan. Compile-Time Techniques for Data Distribution in Distributed Memory Machines. IEEE Transactions on Parallel and Distributed Systems, 2(4):472-482, October 1991.
8. Vivek Sarkar. Automatic Selection of High Order Transformations in the IBM XL Fortran Compilers. IBM Journal of Research and Development, 41(3), May 1997.
9. Vivek Sarkar. Loop Transformations for Hierarchical Parallelism and Locality. Lecture Notes in Computer Science, 1151, 1998. Proceedings of LCR98: Fourth Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers. Held in May 1998 at Carnegie Mellon University, Pittsburgh, PA, USA.
10. Robert Schreiber and Jack Dongarra. Automatic Blocking of Nested Loops. Technical Report 90.38, Research Institute for Applied Computer Science (RIACS), Mountain View, CA, August 1990.
11. Michael E. Wolf and Monica S. Lam. A Data Locality Optimization Algorithm. Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation, pages 30-44, June 1991.
12. Michael J. Wolfe. Optimizing Supercompilers for Supercomputers. Pitman, London and The MIT Press, Cambridge, Massachusetts, 1989. In the series, Research Monographs in Parallel and Distributed Computing.