메뉴 건너뛰기




Volumn 21, Issue 2, 2011, Pages 127-140

Multilayer traffic engineering for energy efficiency

Author keywords

Energy efficiency; Multilayer networks; Multilayer traffic engineering

Indexed keywords

CHIP ARCHITECTURE; CHIP TECHNOLOGY; EFFICIENCY OPTIMIZATION; ENERGY NEEDS; FAST RESPONSE; ICT INFRASTRUCTURES; IP/MPLS; LOGICAL TOPOLOGY RECONFIGURATION; MULTILAYER NETWORKS; MULTILAYER TRAFFIC ENGINEERING; POWER REQUIREMENT; RESOURCE USAGE;

EID: 79956106331     PISSN: 1387974X     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11107-010-0287-6     Document Type: Article
Times cited : (17)

References (16)
  • 2
    • 69249229759 scopus 로고    scopus 로고
    • Multilayer traffic engineering for multiservice environments
    • doi:10.1007/s11107-008-0179-1
    • Puype, B., Colle, D., Pickavet, M., Demeester P.: Multilayer traffic engineering for multiservice environments. Photon. Netw. Commun. 18(2), 150-159 (2009). doi:10.1007/s11107-008-0179-1
    • (2009) Photon. Netw. Commun. , vol.18 , Issue.2 , pp. 150-159
    • Puype, B.1    Colle, D.2    Pickavet, M.3    Demeester, P.4
  • 6
    • 67651162341 scopus 로고    scopus 로고
    • Energy consumption in optical IP networks
    • doi:10.1109/JLT.2008.2010142
    • Baliga, J., Ayre, R., Hinton, K., Sorin, W. V., Tucker, R. S.: Energy consumption in optical IP networks. J. Lightw. Technol. 27(13), 2391-2403 (2009). doi:10.1109/JLT.2008.2010142
    • (2009) J. Lightw. Technol. , vol.27 , Issue.13 , pp. 2391-2403
    • Baliga, J.1    Ayre, R.2    Hinton, K.3    Sorin, W.V.4    Tucker, R.S.5
  • 8
    • 67651148319 scopus 로고    scopus 로고
    • Energy-minimized design for IP over WDM networks
    • doi:10.1364/JOCN.1.000176
    • Shen, G., Tucker, R.: Energy-minimized design for IP over WDM networks. IEEE/OSA J. Opt. Commun. Netw. 1(1):176-186 (2009). doi:10.1364/JOCN.1.000176
    • (2009) IEEE/OSA J. Opt. Commun. Netw , vol.1 , Issue.1 , pp. 176-186
    • Shen, G.1    Tucker, R.2
  • 11
    • 0141896323 scopus 로고    scopus 로고
    • Microarchitectural innovations: Boosting microprocessor performance beyond semiconductor technology scaling
    • Moshovos, A., Sohi G. S.: Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. Proc. IEEE. 89(11), 1560-1575 (2001). doi:10.1109/5.964438 (Pubitemid 33766637)
    • (2001) Proceedings of the IEEE , vol.89 , Issue.11 , pp. 1560-1575
    • Moshovos, A.1    Sohi, G.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.